OASIS-VP-Topic-3 の履歴(No.3)

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  • 1 (2016-05-04 (水) 10:59:52)
  • 2 (2016-05-04 (水) 11:11:27)
  • 3 (2016-05-06 (金) 07:25:43)

OASIS-VP

Overview†

This topic is implementation and evaluation of OpenRISC core.

Research Description†

OpenRISC is an open-source, free RISC core which is provided by the community through OpenCore.org. The OpenRISC project has several features:

• Support 32 and 64 bits instruction set; vector, floating point and DSP instruction.
• Support cache coherence, virtual memory support.
• Available in HDL: Verilog and VHDL.
• ASIC and FPGA implementation proof.

Note: This topic can be extended as an implementation of a full system on FPGA which can interface with mouse, keyboard, VGA and run Linux OS.

Expected Output†

• Investigate the operation and architecture of OpenRISC.
• Implement the OpenRISC core into an FPGA board.
• Evaluate the performance of OpenRISC core.

References†

• Documents: Link

[1] OpenRISC website: http://opencores.org/or1k/Main_Page

[2] Tutorials provided by community: http://openrisc.io/tutorials

[3] Source code, tutorial download: https://github.com/openrisc

[4] Japanese spec: https://github.com/openrisc/or1200/blob/master/doc/openrisc1200_spec_0.7_jp.pdf