OASIS-Project の履歴(No.3)

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• OASIS-Project へ行く。
  • 1 (2014-05-27 (火) 08:57:03)
  • 2 (2014-05-27 (火) 09:23:11)
  • 3 (2014-05-28 (水) 07:58:30)
  • 4 (2014-05-29 (木) 03:54:26)

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OASIS

Contents:

Background†

During the past decade, 3D-Network-on-Chips (3D-NoCs) have been showing their advantages against 2D-NoC systems. At the same time, concerns about their reliability have grown as well due to the different kinds of faults that these systems may encounter. Therefore, 3D-NoC must be fault-tolerant to any kind of permanent failure or run-time malfunction. To achieve this goal, a fault-detection scheme is necessary to discover the presence of fault before the propagation of the fault into the entire system and cause the its collapse.

Previously, 3D-Fault-Tolerant-OASIS (3D-FTO) has been designed. 3D-FTO is able to recover from a large number of faults that can occur at links, input-buffers, and crossbar. However in this system, a fault detection mechanism is absent and the diagnosis of faults rely on assuming the presence of faults at a certain period of time. This make the fault recovery less efficient and diminish the reliability of the system.

In addition, to perform the evaluation logic modules were connected to routers instead of real cores. This approach makes the evaluation less accurate.

Research goal†

• 1. Study OASIS 3D-FTO Router Architecture

• 2. Implement the detection mechanism to be able to detect the faults occurrence with two approaches:

• Source to destination: Flits are checked once arrived to the destination (Network Interface)

• Router to router: Flits are checked at every router (input-buffer) and resent if needed from a hop away distance

• 3. Design the Physical router using Design Compiler (for Synthesis) and SoC Enounter (for Place and route)

• 4. Verify the correctness at each step using ModelSim

• 5. Evaluate the performance of the final 3D Router:

• Hardware complexity (Area, Power, and Speed)

• Performance (Latency, throughput)

• 6. Make the comparison between:

• Source to destination

• Router to router

• 7. Write a thesis

Design Steps and Research plan†

1- Understand the router architecture of 3D-FTO

2- Modify the flit format

3- Decide the code detection and correction algorithm

4- Implement "Source to destination" approach by modifying Okada's Network Interface

5- Implement "Router to router" approach by modifying the Input-port module of the router

6- Evaluation following the design steps illustrated in the figure above

7- Write thesis

Prerequisite†

• Verilog-HDL
• Altera Quartus II
• Altera ModelSim
• Synopsis Design Compiler
• Cadence SoC Encounter

References Set I†

• A CRC Verilog description module for a hard real time communication protocols in a control distributed systems.pdf

• Altera_CRC Compiler User Guide.pdf

• Analysis of Error Recovery Schemes for NoCS.pdf

• Chapter10_Analysis_of_NoC_Error_Recovery_Schems.pdf

• Design and Verification of An Automatic CRC Engine Using Verilog HDL.pdf

• OKADA Network Interface

References Set II†

• Guidance Lectures
• 3D-ONoC-Verilog
• On the Design of a 3D Network-on-Chip for Many-core SoC, Master's Thesis, The University of Aizu. Thesis, slides
• OASIS Network-on-Chip Prototyping on FPGA, Master's Thesis, The University of Aizu. [Thesis], [slides]

Benchmark suite†

• PDF
• ppt