OASIS-8C: Verilog Design and FPGA Prototyping of 8-core OASIS Network-on-Chip System
Project Goal†
- Real design in verilog HDL and prototyping on FPGA of a small scale 8-core OASIS Network-on-Chip System.
- Detailed Design Manual.
Members†
- Nam Khanh Dang
- Akihito Kajikawa
System Architecture†
Specification†
- Network-on-Chip:
- OASIS 3D Network-on-Chip [1].
- Network Interface: ...
- Processing Elements:
Hardware Prototyping Phases†
Schedule†
References†
Last Update:
- 2015 June 8th: Update system architecture diagram.
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