NASH
FPGA Prototyping†
...
Work Phase 1†
- Design Member: The H. Vu
- Description:
- Optimize and evaluation MCN algorithm.
- Merge optimized MCN to FT router and evaluation
- Design MCFT tile.
Work Phase 2†
- Design Member: Y. Murakami
- Description: evaluate hardware complexity of MCFT tile for NASH
- Verilog Source code
Work Phase 3†
Design Member:
Reference†
![[PukiWiki]](image/pukiwiki.png "[PukiWiki]")
sourcecode)
