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Hardware implementations of spiking neural network systems are efficient and effective methods to provide cognitive functions on a chip compared with the conventional stored-program computing style. The challenges that need to be solved toward building such a neuro-inspired computing paradigm with a massive number of synapses include building a small-size massively parallel architecture with low-power consumption, efficient neuro-coding schemes, and lightweight on-chip learning algorithms. In addition, traditional direct neuron-to-neuron interconnection based on a shared-bus is not scalable. Therefore, the above constraints make the deployment of neuro-inspired (brain-like) IC a challenging on-chip interconnect problem, where a balance between scalability and biological real-time requirements needs to be achieved. Our goal in this project is to research and develop an ultra-low-power neuro-inspired spiking massively multicore Chip/SoC based on new deep neuronal algorithms and scalable reconfigurable interconnects. We are researching and developing FPGA and ASIC Chips/SoCs for vision and learning in adaptive autonomous vehicles and mobile land/aerial robots. We are also exploring innovative hardware (i.e., memristor) based low-power circuits for learning on-chip.
To solve the large scale implementation issues of reconfigurability and programmability, a new efficient architecture is required based on a packet-switched network will be developed. NOC is introduced to solve the existing problems in SNN/ANN, such as heavy communication load and lack of reconfigurability. In the proposed system, the weight values and activation functions can be reconfigured as desired. Also, the topology and routing algorithm of the NoC can be changed by sending new data (packets) to satisfies different kinds of SNN. To demonstrate the performance of the algorithms and the system, an FPGA implementation shall be developed and interfaced to a small drone. In addition, a VLSI implementation of the Adaptive (different applications and learning) spiking NASH shall be also developed.
As the desire for realistic spiking neural networks (SNNs) increases, tuning the enormous number of open parameters in these models becomes a difficult challenge. SNNs have been used to model complex neural circuits that explore various neural phenomena such as neural plasticity, auditory systems, vision systems, and many other neural functions. In addition, SNNs are especially well-adapted to run on neuro-inspired hardware that will support biological brain-scale architectures. Although the inclusion of realistic plasticity equations, topologies, and neural dynamics has increased the descriptive power of SNNs, it has also made the task of tuning these biologically realistic SNNs a challenging task. In this research, we present an automated parameter tuning framework capable of tuning SNNs quickly and efficiently using evolutionary algorithms (EA) and readily accessible graphics processing units (GPUs).
The proposed framework is useful for the computational neuroscience and the neuromorphic engineering communities, making the process of constructing and tuning large-scale SNNs much quicker and easier.
Fukuchi-kun, please uplaod the source code here.
=An efficient automated parameter tuning framework for spiking neural networks
ParallelSirial.tar.gz