Vu Huy The の履歴(No.21)

NASH: Neuro-inspired ArchitectureS in Hardware Project

ASL Wiki

Ultra-low Power Spike-based Deep Neural Network System with Scalable Packet-Switched Network

Background, Research Goal, Achievemen, CFPt †

↑

Research schedule†

↑

Step 5 Due date: March 10 13, 2017. (Please prepare .ppt slides and make a presentation)†

Step 5.1
- Describe the overall system organization and Propose a light-weight learning algorithm for NASH System. (NASH stands for 'Neuro-inspired ArchitectureS in Hardware' Project in ASL)

References:

0. Spiking Deep Convolutional Neural Networks for Energy-Efficient Object Recognition, Nov. 2014.

1. A Low-voltage, Low power STDP Synapse implementation using Domain-WallMagnets for Spiking Neural Networks

2. FPGA-based Architecture for Real-time Synaptic Plasticity computation

3. PhD Thesis -Theory of non-linear spike-time-dependent plasticity

4. Demonstration of STDP based Neural Networks on an FPGA

5. Neuron Models on FPGA, Verilog HDL

6.Design of silicon brains in the nano-CMOS era: Spiking neurons,learning synapses and neural architecture optimization, A.S. Cassidy et al. / Neural Networks 45 (2013) 4–26

7. ConvNet Hardware

Step 5.2 Due date: April 30, 2017. Please prepare 8 to 10 pages draft and make a presentation without slides ---> Extended to May 8, 2017.

Draft a conference paper about Acceleration (using FPGA) of Image Recognition with Deep Convolution Neural Network based on FT Packet Switched Network.

Conf. ~~http://www.mcsoc-forum.org/~~ http://www.aiccsa.net/AICCSA2017/

References:

1.Book: FPGA implementation of Neural Netwokrs, 2006
2 CNN on ZynqNet FPGA

↑

RPS†

3/14/2017: Overall System Architecture
3/31/2017: System Architecture

↑

Special RPR (S-RPR)†

~~S-RPR Style: Please read and make a presentation on a day between the 1st-day and last-day of each month until July 2017. Please arrange the schedule and let me know by the second week of each month.~~