VLSI-Design の履歴(No.21)

• 履歴一覧
• 差分 を表示
• 現在との差分 を表示
• ソース を表示
• VLSI-Design へ行く。
  • 1 (2014-06-10 (火) 07:56:50)
  • 2 (2014-06-10 (火) 10:23:53)
  • 3 (2014-06-11 (水) 00:39:48)
  • 4 (2014-06-11 (水) 01:07:46)
  • 5 (2014-06-11 (水) 05:32:27)
  • 6 (2014-06-16 (月) 04:02:07)
  • 7 (2014-06-19 (木) 13:13:43)
  • 8 (2014-06-27 (金) 01:28:31)
  • 9 (2014-06-27 (金) 15:30:46)
  • 10 (2014-06-30 (月) 06:59:12)
  • 11 (2014-07-03 (木) 07:10:10)
  • 12 (2014-07-05 (土) 16:01:01)
  • 13 (2014-07-07 (月) 13:10:01)
  • 14 (2014-07-08 (火) 04:10:56)
  • 15 (2014-07-08 (火) 04:18:05)
  • 16 (2014-07-08 (火) 09:03:57)
  • 17 (2014-07-09 (水) 03:07:28)
  • 18 (2014-07-09 (水) 07:18:49)
  • 19 (2014-07-15 (火) 01:04:52)
  • 20 (2014-07-17 (木) 06:42:51)
  • 21 (2014-10-10 (金) 06:03:56)
  • 22 (2014-10-14 (火) 05:23:51)
  • 23 (2014-10-15 (水) 04:11:51)
  • 24 (2014-11-15 (土) 18:20:57)
  • 25 (2014-12-09 (火) 06:28:18)
  • 26 (2014-12-15 (月) 07:32:16)
  • 27 (2015-01-07 (水) 07:31:40)
  • 28 (2016-11-09 (水) 07:59:19)
  • 29 (2017-10-24 (火) 07:51:26)
  • 30 (2017-10-25 (水) 03:04:50)
  • 31 (2017-10-25 (水) 03:04:50)
  • 32 (2020-06-18 (木) 08:15:56)

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• Technology: 45nm CMOS Process
• Chip Size: ......... Please complete this
• Function: Router for 3D NoC System
• Frequency: ........... Please complete this
• Power Dissipation: 222.387 uW
• Number of Pins: 557
• Completion Date: July 5th (expected)

OASIS 3D Router Tutorials†

1. Synthesis with Design Compiler†

• PPTX, PDF, June 5, 2014.

2. Place & Route with SoC Encounter†

• PPTX, PDF, June 5, 2014.

3 Design Checking: LVS (Layout-Versus-Schematic) and DRC (Design-Rule Check)†

• PPTX, PDF, June 19, 2014.

4 Post Layout Simulation:†

• PPTX, PDF, July 5, 2014.

5 Pad Insertion†

• PPTX, PDF, July 7, 2014.

6. Chip Submission†

• PDF, PPT, Completion Date: July 15th

• Ref. http://www.vtvt.ece.vt.edu/vlsidesign/tutorialCadence_submission.php

PHENIC Control Router†

• 1. Synthesis with Design Compiler
• 2. Place & Route with SoC Encounter
• 3 Design Checking: LVS (Layout-Versus-Schematic) and DRC (Design-Rule Check)
• 4 Post Layout Simulation:
• 5 Pad Insertion
• 6. Chip Submission

Reference: MIPS processor Tutorials†

• Complete tutorial of MIPS processor prototyping on ASIC (in Japanese), zip file

How to Login and use VDEC tools on zxp035†

• To use VDEC tools on zxp035 machine type the following comand in your terminal
  • ssh -X zxp035@zxp035.u-aizu.ac.jp
• Password : blm2011

• To use VDEC tools type:

• design_vision (to use Design Compiler)
• velocity (to use SoC Encounter)
• simvision (to use Simvision)

Registerd IPs @ with VDEC Server†

Links†

• http://aslweb.u-aizu.ac.jp/aslint/index.php?VLSI-Design-Links

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