OASIS-8C System の履歴(No.20) - ASL Wiki

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OASIS-8C Processor of FPGA

Project Goal†

Real design in verilog HDL and prototyping on FPGA of a small scale 8-core OASIS Network-on-Chip System.
Detailed Design Manual.

Target Application: Image Recognition

Members†

Prof. Okuyama

D1 Nam Khanh Dang (d8162103)

System Architecture†

2x2x2 Network-on-Chip:

Network's PE:

Specification†

System specifications:
- OASIS 3D Network-on-Chip [Ref.1].
  - Topology: 3D Mesh.
  - Network's Size: 2x2x2.
  - Document & source code: [Ref.1]
- Network Interface: [Ref.2].
- Processing Elements: (TBD)
  - CPU: MIPS
  - MEM: On-chip (verilog code), Off-chip (see I/O).
  - I/O: Off-chip Memory, Display (LCD, LED), Inter-connection (UART/USB/PCI).
Application specifications:(TBD)
- Target CPU: MIPS.
- Target applications: Image processing (filtering).
Implementation environment:
- Language: Verilog HDL.
- Simulation tool: Modelsim Altera/Cadence Tools.
- Implementation tool: Altera Quartus II/ASIC.
Implementation board: Spartan DE II/CMOS 45 nm.

Hardware Prototyping Tasks†

Task 01: Processor Implemenation (manual)
- Understading the Processor architecture and operation.
- Implementation of I/O accessing operation.
- Simulation and implemenation.
Task 02: Network-Interface Implemenation (manual)
- Establishing an individual network tile: PE(Processing Element) - NI(Network Interface) - R(Router).
- Implemenation local interfacing.
- Implementation on FPGA/ASIC.
Task 03: Network Implementation (manual)
- Establish a 2D 2x2x2 Network Implementation.
- Network simulation.
- Implementation on FPGA/ASIC.
Task 04: Application Implementation (manual)
- Establishing the algorithm base on network's architecture.
- Application demonstration.

Schedule†

Detail of schedule
Step Content Start Date Finish Date Report

1 Design Preparation 2015-June-02 2015-June-30 this page

2 Group first meeting 2015-July-17 2015-July-17

3 Group meeting 2015-Aug-10 2015-Aug-10

Task Assignment (Step 02)

No.	Assignee	Task	Finish Date	Note
1	Khanh	Prepare the schedule of the Project	2015-Jun-19	-
2.1	-	Processor Implemenation	2015-XX-YY	-
2.2	-	Network-Interface Implemenation	2015-XX-YY	-
2.3	-	Network Implemeation	2015-XX-YY	-
2.4	-	Application Implementation	2015-XX-YY	-

References†

[Ref.1]: OASIS Network-on-Chip, Akram Ben Ahmed, Internal-link, Source-code.
[Ref.2]: Network Inteface, R. Okada, Internal-link.
[Ref.3]: FPGA manual (TBU).
[Ref.4]: MIPS_MultiCycle.zip : file://///zxw001/PUBLIC/OASIS-8C/MIPS_MultiCycle.zip

Last Update:

2015 June 8th: Update system architecture diagram.