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Current NoC technology is limited by the speed of their buses. In order to boost the throughput and reduce the power cost of these systems, we intend to implement a Photonic Network on Chip based around the 3D Oasis NoC design.
Most proposed networks are implemented with a dedicated photonic layer stacked on top of conventional electronic layer(s). However, to satisfies future applications with high-bandwidth requirements, single-layer typologies should be modified by increasing the number of wave-guides and MRs in the photonic layer. This technique may not be suitable because of the design limitation in a single photonic router, such as number of wave-guides spacing requirement, higher wave-guides crossing loses, etc. PHENIC implements multi-layer photonic network to deal with these problems.
High-throughput, Reliable Photonic NoC for Many-core Systems
...to be continued
Within about 70 days (RPS on June 13, 2014) of the research you will be asked to prepare a project plan. This plan should identify the tasks to be performed during the research project and sets deadlines for those tasks. The prepared plan will be a topic of discussion of the first RPS meeting between you and your advisor. Note that the research project schedule plan should be updated depending on the progress of your research project.
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