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  • 1 (2017-02-24 (金) 08:46:17)
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Vu Huy The

Oasis†

• OASIS
• ASL Theses
• Nigram Simulator, University of Southampton, UK, http://nirgam.ecs.soton.ac.uk/. SystemC based simulator with configurable NoC parameters.

• Typical Neurochip design evaluation method:
  • (1) Area, power, and timing of the SRAM array could be evaluated with CACTI cache modeling tool
  • (2) Power and timing of the multipliers, adders, and all registers could be evaluated with SPICE
  • (3) The area, power, and timing of the routing core could be evaluated with ORION

Neuromorphic Processors Related Main Papers†

• 1.(2015-MEMRESISTOR) Yongtae Kim, Yong Zhang, Peng Li, A Reconfigurable Digital Neuromorphic Processor with Memristive Synaptic Crossbar for Cognitive Computing, ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issues on Neuromorphic Computing and Emerging Many-Core Systems for Exascale Computing, Volume 11 Issue 4, April 2015 Article No. 38.

• 2.(2011-SRAM) J. s. Seo et al., "A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons," 2011 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, 2011, pp. 1-4. doi: 10.1109/CICC.2011.6055293

• 3.(2010) Janardan Misra, Artificial neural networks in hardware: A survey of two decades of progress, 2010.