Verilog-mode の履歴(No.2)

• 履歴一覧
• ソース を表示
• Verilog-mode は削除されています。
  • 1 (2008-10-16 (木) 09:29:50)
  • 2 (2008-10-16 (木) 11:32:15)

Verilog-mode†

C-c C-h

//-----------------------------------------------------------------------------
// Title         : <title>
// Project       : <project>
//-----------------------------------------------------------------------------
// File          : mipscore.v
// Author        : Daisuke Ohwada  <ohwada@zxp050.u-aizu.ac.jp>
// Created       : 16.10.2008
// Last modified : 16.10.2008
//-----------------------------------------------------------------------------
// Description :
// <description>
//-----------------------------------------------------------------------------
// Copyright (c) 2008 by <company> This model is the confidential and
// proprietary property of <company> and the possession or use of this
// file requires a written license from <company>.
//------------------------------------------------------------------------------
// Modification history :
// 16.10.2008 : created
//-----------------------------------------------------------------------------

M-*

/*
 * 
 */

C-c C-c

/* -----\/----- EXCLUDED -----\/-----
 -----/\----- EXCLUDED -----/\----- */