1. Goal: This project focuses on the research about a novel low power and high performance parallel processor processor based on Queue computation model, where Queue programs are generated by traversing a given data flow graph using level order traversal. The Queue processor uses a circular queue-register to manipulates operands and results, and exploits parallelism dynamically with "little efforts" when compared with conventional architectures. The nonexistence of false dependencies allows programs to expose maximum parallelism that the queue processor can execute without complex and power-hungry hardware such as register renaming and large instruction windows. Parallel processing allows queue processors to speed-up the execution of applications. We are researching and developing a complete tool-chain for this promising computing model consisting of: compiler, assembler, functional and cycle accurate simulator, and hardware design.
This research also focuses on study about Multicore Systems design.
QueueCore Processor's circular Queue-register structure
Public Page
2. Members:
3. Group Publications:
Journal papers
- A. Ben Abdallah, A. Canedo, T. Yoshinga, and M. Sowa, "The QC-2 Parallel Queue Processor Architecture", Journal of Parallel and Distributed Computing, Vol. 68, No. 2, pp. 235-245, 2008.
Conference Papers
- M. Masuda, A. Canedo, A. Ben Abdallah, "Efficient Code Generation Algorithm for Natural Instruction Level Parallelism-aware Queue Architecture," The 19th Intelligent System Symposium (FAN 2009), pp.308-313, Sep. 2009.(Best Presentation Award).
- A. Canedo, A. Ben Abdallah, and M. Sowa, "Compiler Framework for an Embedded 32-bit Queue Processor" , Proc. of the International Conference on Convergence Information Technology (ICCIT07), Gyeongju, South Korea, pp. 877-884, 2007.
- A. Ben Abdallah, T. Yoshinaga, and M. Sowa, "Rapid FPGA Prototyping of a Queue Processor Core for Embedded Computing", Proc. of 67th Conf. of Information Processing Society of Japan, March 2~4, 2005.
- A. Markovskij, M. Sowa, A. Ben Abdallah, S. Shigeta, and T. Yoshinaga, "Design of Producer-Order Parallel Queue Processor Architecture", Proc. of International Workshop on Modern Science and Technology (IWMST 2004), September 2-3, 2004.
- M. Akanda, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, "High performance Hybrid Processor Architecture with Efficient Hardware Usability", Proc. of International workshop on Modern Science and Technology (IWMST 2004), September 2-3, 2004
- A. Ben Abdallah, M. Arsenji, K. Kiuchi, M. Akanda, S. Shigeta, T. Yoshinaga, and M. Sowa, "PQPpfB: Parallel Queue Processor Architecture in Verilog-HDL", Proc. of 66th Information Processing Society of Japan, pp. 3F-4, March 2004.
- A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, "Reduced Bit-Width Instruction Set Architecture for Q-mode Execution in Hybrid Processor Architecture (FaRM-rq)", Proc. of Information Processing Society of Japan, pp. 19-23, June 2003.
- A. Ben Abdallah, K. Nikolova, and M. Sowa, "FARM-Queue Execution Model: Towards an Alternative Computing Paradigm", Proc. of IPSJ Symposium, Yokohama pp.99-100, March 2000.
- A. Ben Abdallah, M. Sarem., and M. Sowa, "Acyclic DFG on a Queue Machine", Proc. of JSPP, Tokyo, pp.119-120, 2000.
- Hiroki Hoshino, Abderazek Ben Abdallah and Kenichi Kuroda. Advanced Optimization and Design Issues of a 32-bit Embedded Processor Based on Produced Order Queue Computation Model, IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, Shanghai, pp.16-22, Dec. 2008.
- A. Ben Abdallah, et. all "Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core", International Conference on Embedded and Ubiquitous Computing (EUC2005), LNCS Vol.3824, pp. 340-349, 2005
- A. Ben Abdallah, et. all,"Queue Processor for Novel Queue Computing Paradigm Based on Produced Order Scheme", IEEE computer Society, Proc. of the The 7th High Perfomance Computing and Grid in Asia Pacific Region (HPCAsia2004), pp. 169-177, July 2004.
Technical Reports:
- H. Hoshino, QSoC - Queue System on Chip on FPGA, Technical Report, ASL Systems Architecture Group, School of Computer Science and Engineering, The University of Aizu, Jan. 2010.
- H. Hoshino, QC-2 Data Path, Technical Report, ASL Systems architecture Group, School of Computer Science and Engineering, The University of Aizu, Oct. 2009
- A. Ben Abdallah, QueueCore - The Strong Wave!, Technical report, Network Computing Laboratory, Graduate School of Information Systems, The University of Electro-communications, May 2007
- A. Ben Abdallah, QueueCore Instruction Set Architecture,Technical Report, Parallel/Distributed Systems Laboratory, Graduate School of Information Systems, National University of Electro-communications, January 2003.
- A. Ben Abdallah, QC-1 Processing Stages Algorithms,
Technical Report, Parallel/Distributed Systems Laboratory, Graduate School of Information Systems, National University of Electro-communications, 2003.
4. Related sub-research:
5. Sponsors:
- National University of Electro-communications, Tokyo. (Budget: GB)
6. Poster
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