OASIS-Project の履歴(No.2)

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• OASIS-Project へ行く。
  • 1 (2014-05-27 (火) 08:57:03)
  • 2 (2014-05-27 (火) 09:23:11)
  • 3 (2014-05-28 (水) 07:58:30)
  • 4 (2014-05-29 (木) 03:54:26)

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OASIS

Contents:

Background†

During the past decade, 3D-Network-on-Chips (3D-NoCs) have been showing their advantages against 2D-NoC systems. At the same time, concerns about their reliability have grown as well due to the different kinds of faults that these systems may encounter. Therefore, 3D-NoC must be fault-tolerant to any kind of permanent failure or run-time malfunction. To achieve this goal, a fault-detection scheme is necessary to discover the presence of fault before the propagation of the fault into the entire system and cause the its collapse.

Previously, 3D-Fault-Tolerant-OASIS (3D-FTO) has been designed. 3D-FTO is able to recover from a large number of faults that can occur at links, input-buffers, and crossbar. However in this system, a fault detection mechanism is absent and the diagnosis of faults rely on assuming the presence of faults at a certain period of time. This make the fault recovery less efficient and diminish the reliability of the system.

To be continued

Research goal†

The main goal of this research is to design and implement a fault detction and correction scheme for 3D-Fault-Tolerant-OASIS (3D-FTO). The scheme is based on Error-Detection-Codes (EDC) and Error-Correction-Codes (ECC). It should detect the presence of any kind of errors or malfunction and make the necessary communications with the different modules of 3D-FTO to perform the quick recovery ensuring a graceful performance degradation as less as possible.

Research plan†

• Investigate about the different approaches for fault detection in NoC systems

• Understand 3D-FTO architecture.

• Modify the flit format to host the additional code portion for fault detection and correction.

• Make the necessary modification for the remaining modules of the router.

• Evaluate the performance of the scheme (Area, power, latency, ...)

To be continued

Prerequisite†

• Verilog-HDL
• Altera Quartus II
• Altera ModelSim
• Synopsis Design Compiler
• Cadence SoC Encounter

References Set I†

• A CRC Verilog description module for a hard real time communication protocols in a control distributed systems.pdf

• Altera_CRC Compiler User Guide.pdf

• Analysis of Error Recovery Schemes for NoCS.pdf

• Chapter10_Analysis_of_NoC_Error_Recovery_Schems.pdf

• Design and Verification of An Automatic CRC Engine Using Verilog HDL.pdf

• OKADA Network Interface

To be continued

References Set II†

• Guidance Lectures
• 3D-ONoC-Verilog
• On the Design of a 3D Network-on-Chip for Many-core SoC, Master's Thesis, The University of Aizu. Thesis, slides
• OASIS Network-on-Chip Prototyping on FPGA, Master's Thesis, The University of Aizu. [Thesis], [slides]

To be continued

Benchmark suite†

• PDF
• ppt