OASIS Code†
Benchmark suite†
- JPEG
- Matrix multiplication
- Transpose traffic pattern
- Uniform traffic pattern
Blogs†
Simulators†
1. NoC prototypes: full design data available†
Here is a list of past and current NoC prototyping efforts either on FPGAs or as VLSI circuits. If you know of others and wanted them listed here please let me know. These are efforts where design data are publicly available:
2. NoC prototypes: partial/no/promised design data available†
Here is a list of people, publications, or pointers to reported NoC prototypes; however, no complete design data are publicly available:
- Atlas (GAPH, PUCRS, Brazil. One can simulate different NoC topologies and generate VHDL files, which then could be synthesized. The authors reported FPGA implementation.) – 2011
- NoCGen: an environment for the Hermes NoC emulation (Grenoble Institute of Technology). NoCGen uses the Hermes NoC developed by the PUCRS of Porte Allegre, Brazil. – FPGA, 2011
- NoCBench, Tampere University of Technology. Only limited design data are available. That includes some libs too.) – 2009.
3. Router prototypes†
Here is a list of efforts that focused on the router architecture. VHDL/Verilog implementations available.
3D Packaging In Japan†
Mis†
NoC2006 Keynotes
- Advances in On-Chip Interconnects (invited presentations)
Chair: Pol Marchal, IMEC, Belgium
NOCS 2011: The Fifth ACM/IEEE International Symposium on Networks-on-Chip
Keynotes:
- Integrating the Network: Why It Matters
Tryggve Fossum, Director of Microarchitecture Development, Intel
Last update: Feb. 20, 2014.
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