OASIS-8C: Verilog Design and FPGA Prototyping of 8-core OASIS Network-on-Chip System
Project Goal†
- Real design in verilog HDL and prototyping on FPGA of a small scale 8-core OASIS Network-on-Chip System.
- Detailed Design Manual.
Members†
- Nam Khanh Dang
- Akihito Kajikawa
System Architecture†
...
Specification†
Hardware Prototyping Phases†
Schedule†
References†
![[PukiWiki]](image/pukiwiki.png "[PukiWiki]")
