OASIS: Network-on-Chip Project
Project Description:†
Future embedded and general purpose processor architectures will be implemented as multicore systems with nanoscale technology consisting of hundreds of processing and storage elements. These multicore systems are emerging as a key design solution for today's nanoelectronics design problems. The interconnection structure supporting such systems will be closer to a sophisticated network than to current bus-based solutions. Such network must provide high throughput and low latency while keeping area and power consumption low.
Our research efforts is about solving several design challenges to enable such new paradigm in Multicore Systems. In particular, we are investigating implementation techniques for basic building blocks, new topologies, flow control techniques, and low-latency, high-throughput/fault-tolerant routing algorithms.
Members†
Former Members:
Group Publications†
- A. Ben Ahmed, A. Ben Abdallah, K. Kuroda,Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC, IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), pp.67-73, Nov. 2010. (best paper award)
(Slides), (Papers)
- K. Mori, A. Esch, A. Ben Abdallah, K. Kuroda, Advanced Design Issues for OASIS Network-on-Chip Architecture, IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010),pp.74-79, Nov. 2010. (Slides); (Paper)
- A. Ben Abdallah, T. Yoshinaga and M. Sowa, "Mathematical Model for Multiobjective Synthesis of NoC Architectures", IEEE Proc. of the 36th International Conference on Parallel Processing, Sept. 4-8, 2007. (PDF)
- A. Ben Abdallah, Masahiro Sowa, "Basic Network-on-Chip Interconnection for Future Gigascale MCSoCs Applications: Communication and Computation Orthogonalization", JASSST2006, Dec. 4-9th, 2006. (PDF)
- T. Uesaka, OASIS NoC Topology Optimization with Short-Path Link, Technical Report, Systems Architecture Group,March 2011.PDF
- K. Mori, A. Ben Abdallah, OASIS NoC Architecture Design in Verilog HDL, Technical Report,TR-062010-OASIS, Adaptive Systems Laboratory, the University of Aizu, June 2010.
PDF
Theses:
- Shuu Endou, Hardware Prototyping and Evaluation of Distributed Routing Core Network-Interface for OASIS NoC Architecture, Bachelor Thesis, School of Computer Science and Engineering,The University of Aizu, Feb. 2013 (slides)
Sponsors†
- The University of Aizu, Competitive Research Funding.
POSTER†
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OASIS Code†
Benchmark suite†
- JPEG
- Matrix multiplication
- Transpose traffic pattern
- Uniform traffic pattern
Blogs†
Simulators†
1. NoC prototypes: full design data available†
Here is a list of past and current NoC prototyping efforts either on FPGAs or as VLSI circuits. If you know of others and wanted them listed here please let me know. These are efforts where design data are publicly available:
2. NoC prototypes: partial/no/promised design data available†
Here is a list of people, publications, or pointers to reported NoC prototypes; however, no complete design data are publicly available:
- Atlas (GAPH, PUCRS, Brazil. One can simulate different NoC topologies and generate VHDL files, which then could be synthesized. The authors reported FPGA implementation.) – 2011
- NoCGen: an environment for the Hermes NoC emulation (Grenoble Institute of Technology). NoCGen uses the Hermes NoC developed by the PUCRS of Porte Allegre, Brazil. – FPGA, 2011
- NoCBench, Tampere University of Technology. Only limited design data are available. That includes some libs too.) – 2009.
3. Router prototypes†
Here is a list of efforts that focused on the router architecture. VHDL/Verilog implementations available.
3D Packaging In Japan†
Last update: ABA, Feb. 20, 2014.
![[PukiWiki]](image/pukiwiki.png "[PukiWiki]")
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