Ben A. Abderazek Group /Documents の履歴(No.2)

Documents†

PNoC: Design and Preliminary Evaluation of a Parameterizable NoC for MCSoC Generation and Design Space Exploration, The 19th Intelligent System Symposium (FAN 2009), pp.314-317, Sep.2009 PAPER,SLIDES

Design and Evaluation of a Complexity Effective Network-on-Chip Architecture on FPGA, The 19th Intelligent System Symposium (FAN 2009), pp.318-321, Sep. 2009. PAPER,SLIDES

Embedded MCSoC Architecture and Period-Peak Detection (PPD) Algorithm for ECG/EKG Processing, The 19th Intelligent System Symposium (FAN 2009), pp.298-303, Sep. 2009. PAPER,SLIDES

Efficient Code Generation Algorithm for QueueCore Architecture, The 19th Intelligent System Symposium (FAN 2009), pp.308-313, Sep. 2009 PAPER,SLIDES

Single Instruction Dual-Execution Model Processor Architecture, IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, Shanghai, pp.30-36, Dec. 2008 PAPER,SLIDES],

Advanced Optimization and Design Issues of a 32-bit Embedded Processor Based on Produced Order Queue Computation Model, IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, Shanghai, pp.16-22, Dec. 2008 PAPER ,SLIDES . .

The QC-2 Parallel Queue Processor Architecture, Journal of Parallel and Distributed Computing, Vol. 68, No. 2, (2008), pp. 235– 245. PAPER,

Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core", International Conference on Embedded and Ubiquitous Computing (EUC2005), LNCS Vol.3824, pp. 340-349, 2005 PAPER,SLIDES

Queue Processor for Novel Queue Computing Paradigm Based on Produced Order Scheme, IEEE computer Society, Proc. of the The 7th High Perfomance Computing and Grid in Asia Pacific Region (HPCAsia2004), pp. 169-177, July 2004.

QC-1 Processing Stages Algorithms,Technical Report, Ref: TRQC1PSA03, UEC, IS, October

Graph Transformation Methods and Theoretical Performance Evaluation of Queue Computation Models , Masashi Masuda, The Univ. of Aizu, Feb. 12, 2009. &ref(): File not found: "s1130209_GT2008.pdf" at page "Ben A. Abderazek Group";
Advanced Hardware Optimization Algorithms for High Performance Queue Processor Architecture, Hiroki Hoshino, The Univ. of Aizu, Feb. 12, 2009. &ref(): File not found: "s1130198_GT2008.pdf" at page "Ben A. Abderazek Group";
Research on Hardware Design of Dual-Mode Processor Architecture, Taichi Maekawa, The Univ. of Aizu, Feb. 12, 2009. &ref(): File not found: "s1130205_thesis.pdf" at page "Ben A. Abderazek Group";