Available Research Topics の履歴(No.2) - ASL Wiki

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Available Research Topics

OASIS-VP: Fault-tolerant Many-core Mobile Vision System†

GT 1. Multicore Image Processing System based on OASIS NoC
- Ref.:
  - Phython http://pythonvision.org/basic-tutorial/
  - Modelsim/MATLAB Co-simulation of a QoS Multi-Core Image Processing System using on-Chip Interconnect.

GT 2. Performance Evaluation of low-level vision processing algorithms
- Ref.:

GT 3. Study of Real-Time low-level vision processing algorithms on FPGA
- Ref.:

MS 1. FPGA Implementation of Real-Time SIFT Algorithm for Image Recognition based on QSoC/NoC

Ref.:

PHENIC: Si-Photonics NoC†

GT 1. Power and Performance Comparison of 2D-Electronic NoC and 2D-Opto-Electronic NoC

Ref.
- A.Ben Ahmed, M.Meyer, Y.Okuyama, A.Ben Abdallah, "Efficient Router Architecture, Design and Performance Exploration for Many-core Hybrid Photonic Network-on-Chip (2D-PHENIC)", submitted to the 2014 International Conference on Information Science and Control Engineering ICISCE 2015, Shanghai, China, April 24-26, 2014 (Latex) (PDF)

Achraf Ben Ahmed, A. Ben Abdallah, PHENIC: Towards Photonic 3D-Network-on-Chip Architecture for High-throughput Many-core Systems-on-Chip, IEEE Proceedings of the 14th International conference on Sciences and Techniques of Automatic control and computer engineering, Dec. 2013. DOI

GT 2. Design of Opto-Electronic Network-Interface for PHENIC System

Achraf Ben Ahmed, Akram Ben Ahmed, A. Ben Abdallah, Novel Si-Photonics Network-on-Chip for Future Generations of Many-core Systems-on-Chip, submitted to (Journal of Parallel and Distributed Computing)(PDF),(Latex) Update date: May.1, Time: 1:02.

Achraf Ben Ahmed, Akram Ben Ahmed, Y.Okuyama, A. Ben Abdallah, Low-overhead Path-setup Algorithm for Energy-efficient Hybrid Silicon-Photonic Network-on-Chip Systems, submitted to The IEEE 7th International Conference on Awareness Science and Technology (ICAST 2015) (PDF , Latex) Update date: May.14, Time: 20:57.

OASIS: Reliable Network-on-Chip†

5. Design and Evaluation of Efficient Error Detection Mechanism for OASIS 3D-NoC, B4 Mitsunari Ishii

6. Design and Evaluation of 3D-OASIS-NoC Matrix Processor, M1 Mitsuhiro Nakamura

7. Design and Evaluation of 3D OASIS Router with Through-Silicon-Via (TSV), B4 Yuki Tanaka

8. Error Detection & Correction Mechanism Based on Router-to-Router Approach