Michael Meyer

Fault-tolerant Photonic Network-on-Chip for Reliable Many-core Systems-on-Chip (tentative)

Schedule

SectionCompletion DateDraft
AbstractJuly 22, 10 AMAbstract.pdf
IntroductionJuly 27, 10 AMIntroduction
Related WorkAugust 3, 6 PMRelated Work.pdf
System ArchitectureAugust 10, 10 AMSystem Architecture_v1.pdf
Routing AlgorithmAugust 11, 10 AMRouting Algorithm_v1.pdf
Design Space ExplorationAugust 19, 10 AMDesign Space Exploration_v1.pdf
EvaluationAugust 31 August 27, 10 AMEvaluation+v1.pdf
Conclusion and Future WorkSept 4, 10 AMConclusion and Future Work.pdf

0. Abstract

1. Introduction

2. Related work

3. System Implementation

Notes:

4. FT Router design Space Exploration

5. Evaluation

Ref. 1 Crosstalk noise and bit error rate analysis for optical network-on-chip

Similar to Ref. 1, Develop your won Mathematical Model and calculate these values (cross-talk, SNR, BER). Do not use CLAP tool.

IMPORTANT NOTES

5. Conclusions and Future Work

References


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