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The biological brain implements massively parallel computations using a complex architecture that is different from current Von Neuman machine. Our brain is a low-power, fault-tolerant, and high-performance machine! It consumes only about 20W and brain circuits continue to operate as the organism needs even when the circuit (neuron, neuroglia, etc.) is perturbed or died. Conventional neural networks encode information with static input coding, eg. encoding a pattern as 0011 (binary bits) for 4 input neurons, and another pattern 0010. While in SNN, besides the pattern code, the time-related factors, eg. spiking rate, spiking rank and spiking intervals, can be used to present the information. This greatly increases the information processing capacity of a neural network. SNN only process information when spikes occur. As a result, SNNs consume almost no energy when no spikes occur [www]. A biological SNN (e.g. mammalian brains) uses a spike rate of only several KHz to finish a complex task (e.g. vision pattern recognition) with each spike consumes an energy of in fJ per synapse. Spiking neural network (SNN) simulations are a flexible and powerful method for investigating the behavior of neuronal systems. However, simulation of the spiking neural networks in software is slow. An alternative approach is a hardware implementation of such system, which provides the possibility to generate independent spikes accurately and simultaneously output spikes in real time. Also, spiking neural network can take full advantage of hardware inherent parallelism. SNN and ANN are widely used in signal processing, speech synthesis, pattern recognition, and so forth.
To solve the large scale implementation issues of reconfigurability and programmability, a new efficient architecture is required based on a packet-switched network will be developed. NOC is introduced to solve the existing problems in SNN/ANN, such as heavy communication load and lack of reconfigurability. In the proposed system, the weight values and activation functions can be reconfigured as desired. Also, the topology and routing algorithm of the NoC can be changed by sending new data (packets) to satisfies different kinds of SNN. To demonstrate the performance of the algorithms and the system, an FPGA implementation shall be developed and interfaced to a small drone. In addition, a VLSI implementation of the Adaptive (different applications and learning) spiking NASH shall be also developed.
As the desire for realistic spiking neural networks (SNNs) increases, tuning the enormous number of open parameters in these models becomes a difficult challenge. SNNs have been used to model complex neural circuits that explore various neural phenomena such as neural plasticity, auditory systems, vision systems, and many other neural functions. In addition, SNNs are especially well-adapted to run on neuro-inspired hardware that will support biological brain-scale architectures. Although the inclusion of realistic plasticity equations, topologies, and neural dynamics has increased the descriptive power of SNNs, it has also made the task of tuning these biologically realistic SNNs a challenging task. In this research, we present an automated parameter tuning framework capable of tuning SNNs quickly and efficiently using evolutionary algorithms (EA) and readily accessible graphics processing units (GPUs).
The proposed framework is useful for the computational neuroscience and the neuromorphic engineering communities, making the process of constructing and tuning large-scale SNNs much quicker and easier.
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