OASIS: Reliable Network-on-Chip Project
Project Description:†
Future embedded and general-purpose processors will be implemented as multicore systems with nanoscale technology consisting of hundreds of processing and storage elements. These multicore systems are emerging as a key design solution for today's nanoelectronics design problems. The interconnection structure supporting such systems will be closer to a sophisticated network than to current bus-based solutions. Such network must provide high throughput and low latency while keeping area and power consumption low.
Our research efforts is about solving several design challenges to enable such new paradigm in Multicore Systems. In particular, we are investigating implementation techniques for basic building blocks, new topologies, flow control techniques, and low-latency, high-throughput/fault-tolerant routing algorithms.
Members†
Group Publications†
- Mitsunari Ishii, Architecture and Design of an Efficient Router for OASIS 3D Network-on-Chip System, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2015. Thesis.pdf
- Yuuki Tanaka, Design and Evaluation of Efficient Error Detection Mechanism for OASIS 3D-NoC, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2015. Thesis.pdf,
- Akram Ben Ahmed, High Throughput Architecture and Routing Algorithms Towards the Design of Reliable Many-Core Network-on-Chip Systems, Doctoral Thesis Preliminary Presentation, October 20, 2014. [slides.pptx]
- A. Ben Ahmed, M. Meyer, Y. Okuyama, and A. Ben Abdallah, Adaptive Error- and Traffic Aware Router Architecture for 3D Network-on-Chip Systems , IEEE Proceedings of the 8th International Symposium on Embedded Multicore/Many-core SoCs (MCSoC-14), pp. 197-2014, Sept. 2014.
- A. Ben Ahmed, A. Ben Abdallah, OASIS 3D-Router Hardware Physical Design, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, July 8, 2014.
- Akram Ben Ahmed, Achraf Ben Ahmed, A. Ben Abdallah, Deadlock-Recovery Support for Fault-tolerant Routing Algorithms in 3D-NoC Architectures, IEEE Proceedings of the 7th International Symposium on Embedded Multicore/Many-core SoCs (MCSoC-13), pp., 2013.
[DOI]
- Akram Ben Ahmed, T. Ouchi, S. Miura, A. Ben Abdallah, Run-Time Monitoring Mechanism for Efficient Design of Application-specific NoC Architectures in Multi/Manycore Era, IEEE Proc. of the 6th International Workshop on Engineering Parallel and Multicore Systems (ePaMuS2013'), July 2013.
[DOI]
- Akram Ben Ahmed, T. Ouchi, S. Miura, A. Ben Abdallah, Run-Time Monitoring Mechanism for Efficient Design of Application-specific NoC Architectures in Multi/Manycore Era, Proc. IEEE 6th International Workshop on Engineering Parallel and Multicore Systems (ePaMuS2013'), July 2013.
- Akram Ben Ahmed, A. Ben Abdallah, Low-overhead Routing Algorithm for 3D Network-on-Chip, IEEE Proc. of the The Third International Conference on Networking and Computing (ICNC'12), pp. 23-32, 2012.
[DOI]
- Akram Ben Ahmed, A. Ben Abdallah, LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture, '''IEEE Proceedings of the 6th International Symposium on Embedded Multicore SoCs (MCSoC-12), pp. 167-174, 2012.
[DOI]
- Akram Ben Ahmed, A. Ben Abdallah,
ONoC-SPL Customized Network-on-Chip (NoC) Architecture and Prototyping for Data-intensive Computation Applications, '''IEEE Proceedings of The 4th International Conference on Awareness Science and Technology, pp. 257-262, 2012.
DOI
- Kenichi Mori,A. Ben Abdallah, OASIS Network-on-Chip Prototyping on FPGA, Master's Thesis, The University of Aizu, Feb. 2012. [Thesis], [slides]
- Ben Ahmed Akram, A. Ben Abdallah,[[On the Design of a 3D Network-on-Chip for Many-core SoC, Master's Thesis, The University of Aizu, Feb. 2012.
[Thesis], [slides]
- Shohei Miura, A. Ben Abdallah, Design of Parametrizable Network-on-Chip, Master's Thesis, The University of Aizu, Feb. 2012.
- A. Ben Ahmed, A. Ben Abdallah, K. Kuroda,Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC, IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), pp.67-73, Nov. 2010. (best paper award)
(Slides), (Papers)
- K. Mori, A. Esch, A. Ben Abdallah, K. Kuroda, Advanced Design Issues for OASIS Network-on-Chip Architecture, IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010),pp.74-79, Nov. 2010. (Slides); (Paper)
- A. Ben Abdallah, T. Yoshinaga and M. Sowa, "Mathematical Model for Multiobjective Synthesis of NoC Architectures", IEEE Proc. of the 36th International Conference on Parallel Processing, Sept. 4-8, 2007. (PDF)
- T. Uesaka, OASIS NoC Topology Optimization with Short-Path Link, Technical Report, Systems Architecture Group,March 2011.PDF
- K. Mori, A. Ben Abdallah, OASIS NoC Architecture Design in Verilog HDL, Technical Report,TR-062010-OASIS, Adaptive Systems Laboratory, the University of Aizu, June 2010.
PDF
- A. Ben Abdallah, Masahiro Sowa, "Basic Network-on-Chip Interconnection for Future Gigascale MCSoCs Applications: Communication and Computation Orthogonalization", JASSST2006, Dec. 4-9th, 2006. (PDF)
Theses:
- A. Ben Ahmed, High-throughput Architecture and Routing Algorithms Towards the Design of Reliable Mesh-based Many-Core Network-on-Chip Systems, PhD Thesis, Graduate School of Computer Science and Engineering, University of Aizu, March 2015. Thesis.pdf
- Mitsunari Ishii, Architecture and Design of an Efficient Router for OASIS 3D Network-on-Chip System, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2015. slides.pdf, Thesis.pdf
- Yuuki Tanaka, Design and Evaluation of Efficient Error Detection Mechanism for OASIS 3D-NoC, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2015. slides.pdf, Thesis.pdf
- Shuu Endou, Hardware Prototyping and Evaluation of Distributed Routing Core Network-Interface for OASIS NoC Architecture, Bachelor Thesis, School of Computer Science and Engineering,The University of Aizu, Feb. 2013 (slides)
Technical Reports and Tutorials†
- A. Ben Ahmed, A. Ben Abdallah, OASIS 3D-Router Hardware Physical Design, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, July 8, 2014.
Verilog Code†
Benchmark suite†
References:†
TSV†
1.(2014) TSV-to-TSV Inductive Coupling-Aware Coding Scheme for 3D Network-on-Chip, Ashkan Eghbal, Pooria M.Yaghini, Siavash S.Yazdi, and Nader Bagherzadeh
Department of Electrical Engineering and Computer Science, University of California, Irvine.
2. (2013) A Low-overhead Fault Tolerance Scheme for TSV-based 3D Network on Chip Links, Igor Loi, , Subhasish Mitra,Thomas H. Lee, Shinobu Fujita, and Luca Benini, DEIS, University of Bologna, Bologna, Italy,Stanford University, California, Usa,Toshiba, San Jose, CA, USA (Kawasaki, Kanagawa, Japan)
3. Session 8: Emerging Technologies, Local copy.
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