Fault-tolerant 3D-NoC-based Spiking Neuromorphic System/Chip with Light-weight On-chip Learning
Research Background†
Please complete this section
Research Goal†
The goal of this Doctoral thesis is to research and implement a Deep Spiking Neural Network Architecture with on-chip learning scheme and based on the previously developed schemes NASH1
The expected outputs from this research are:
- (1) An efficient adaptive configuration method which enables reconfiguration of different SNN parameters (spike weights, routing, hidden layers, topology, etc.)
- (2) An Efficient Multicast Fault-tolerant Routing Algorithm for the neurochip
- (3) Efficient on-chip learning Algorithm
- (4) To demonstrate the performance of the algorithms and the system, an FPGA implementation shall be developed and evalauted with several biological SNNs. In addition, a VLSI implementation shall be also developed.
Research schedule†
===> April 1, 2019 to July 31, 2019
August 9 (Fri), 2019. Time: 4:00 PM†
Reading 3: Spiking Neural Networks Hardware Implementations and Challenges: A Survey, ACM Journal on Emerging Technologies in Computing Systems (JETC), 2019
- Summary (08/21/2019, Time:02:56 PM)
(pdf, pptx.)
July 31 (Wed) August 26, 2019.†
Achievement†
On-going Conference and Jnl papers†
Conferences†
- Draft_v1.1 (08/21/2019, Time:02:28 PM)
(latex, pdf)
- Draft_v1.2 (08/23/2019, Time:02:28 PM)
(latex, pdf)
- Draft_v1.3 (08/21/2019, Time:08:27 PM)
(latex, pdf)
- Draft version ?
Journals†
none
Survey reports†
none
Doctoral Dissertation†
none
Update History†
- May 6, 2019: Schedule updtaed, by B.
- April 17, 2019: Page created, by B.