Design and Analysis of Electrical Control Router for Hybrid Photonics NoC System

Background (Problem Definition)

The huge computing power of many-core multi-processor systems will require very large on-chip and off-chip data transfer rates (> 100TB/s). One efficient technology for transmitting this level of information is the optical interconnects, which promise significant advantages over their electronic counterparts. In particular, optical on-chip interconnect (ONoC)) offers a potentially disruptive technology solution with fundamentally low power dissipation that remains independent of capacity while providing ultra-high throughput and minimal access latency. In addition, when combined with 3D integration technology, ONoC offers advantages over 2D NoC design, such as shorter wire length, higher packing density, and smaller footprint.

Current PHENIC and also conventional Photonic NoC Systems lack an efficient control router.

Research Goal

Hardware design and evaluation of Electrical Control Router for Photonic Network-on-Chip Systems.

Research Schedule

Step 0 (Mentor: D3 Achraf), Completion Date: 7/24

Step 1 Completion Date: July 30, August 10, 2015.

Read these references:

Step 2 Completion Date: September 20, 2015.

Run these 2 tutorials on your machine:

Step 3 Due date: October 30, 2015.

CR Design

Step 4 Due date: November 30,2015.

CR Evaluation

Step 5

Thesis writing

References

Verilog Code


トップ   新規 一覧 検索 最終更新   ヘルプ   最終更新のRSS