Available Research Topics の履歴(No.14)

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  • 1 (2015-05-15 (金) 05:14:14)
  • 2 (2015-05-15 (金) 12:13:00)
  • 3 (2015-05-16 (土) 03:12:20)
  • 4 (2015-05-19 (火) 00:49:42)
  • 5 (2015-05-20 (水) 09:57:29)
  • 6 (2015-05-23 (土) 14:01:41)
  • 7 (2015-05-24 (日) 05:22:09)
  • 8 (2015-05-24 (日) 13:48:03)
  • 9 (2015-06-06 (土) 03:43:28)
  • 10 (2015-06-06 (土) 03:43:28)
  • 11 (2015-06-07 (日) 08:45:58)
  • 12 (2015-06-08 (月) 05:13:46)
  • 13 (2015-06-08 (月) 06:15:05)
  • 14 (2015-06-25 (木) 05:01:54)
  • 15 (2015-07-07 (火) 07:36:56)
  • 16 (2015-12-07 (月) 10:00:16)
  • 17 (2016-05-03 (火) 06:50:15)
  • 18 (2016-05-05 (木) 23:48:35)
  • 19 (2016-05-08 (日) 00:04:46)
  • 20 (2016-05-08 (日) 04:16:59)
  • 21 (2016-05-08 (日) 11:42:55)
  • 22 (2016-05-09 (月) 08:51:14)
  • 23 (2016-05-09 (月) 08:51:14)
  • 24 (2016-05-10 (火) 11:03:51)
  • 25 (2016-05-18 (水) 07:12:24)
  • 26 (2016-05-23 (月) 02:41:26)
  • 27 (2016-05-23 (月) 10:16:00)
  • 28 (2016-05-24 (火) 04:10:02)
  • 29 (2016-05-24 (火) 10:20:53)
  • 30 (2016-05-25 (水) 00:15:12)
  • 31 (2016-05-25 (水) 03:35:54)
  • 32 (2016-05-25 (水) 23:47:29)
  • 33 (2016-05-26 (木) 07:35:50)
  • 34 (2016-05-26 (木) 10:01:18)
  • 35 (2016-05-27 (金) 03:30:23)
  • 36 (2016-05-30 (月) 08:09:18)
  • 37 (2016-06-01 (水) 09:52:26)
  • 38 (2016-06-03 (金) 05:27:07)
  • 39 (2016-06-06 (月) 01:31:32)
  • 40 (2016-11-09 (水) 07:59:18)
  • 41 (2016-11-09 (水) 11:15:49)
  • 42 (2016-12-04 (日) 00:58:09)
  • 43 (2017-02-07 (火) 06:04:53)
  • 44 (2017-03-09 (木) 06:24:13)

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PHENIC:Si-Photonics Netwok-on-Chip ==> Go to PHENIC Project Page†

3. Design of High-speed Optical Router Architecture for PHENIC Many-core Systems†

OASIS: Reliable Network-on-Chip ==>go to OASIS Project Page†

4. Design and Evaluation of 3D OASIS Router with Through-Silicon-Via (TSV)†

Efficient Error Detection and Correction Mechanism for OASIS Network-on-Chip System†

Processing Cores for Adaptive computing †

Adaptive Processor†

5. Implementation of task assignment algorithm†

Implementation of architecture (Ishikuro)†

Matrix Processor†

6. Layout design of Matrix-ALU†

Practical interface between host computer/routers (Nakamura)†

Embedded navigation system as a practical application (Yusuke)†

Advanced Vision Processing Algorithms†

Architecture exploration of 2DCDP for 3D-chips†

7. Video recognition with TSCDP (Hayamizu)†

Real Time Signal Processing†

Extraction of training efficiency from EEG (Ito)†

8. P300 detection from few electrodes†

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• Design and Evaluation of Efficient Error Detection Mechanism for OASIS 3D-NoC, B4 Mitsunari Ishii

• Design and Evaluation of 3D-OASIS-NoC Matrix Processor,

• Performance Study and Evaluation of OASIS Network-on-Chip on FPGA)