Takaya Hirai の履歴(No.13)

Complexity and Performance Evaluation of OASIS 3D-Router

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- ID: s1200022

Background (Problem Definition)†

During this last decade, 3D- Network-on-Chips (3D-NoCs) have been proposed as a promising solution for future systems on chip design. It offers more scalability, higher bandwidth, and less interconnect-power than the 2D-NoC architectures.

One of the major issues in 3D-NoC systems is how to verify the system correctness and integrity. 3D-NoC architecture research includes a lot of trade-offs between topology, routing, flow control, buffer size, packet size, and other optimization techniques. It is difficult to analyze these trade-offs using only high-level simulations.

Previously, 3D-OASIS- NoC (3D-ONoC) has been designed. 3D-FTO showed great performance under real benchmarks and synthetic traffic patterns [1]. However, logic modules were connected to routers instead of real cores. This make the evaluation less accurate.

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Research goal†

The main goals of this research are:

1. Study OASIS 3D Router Architecture

2. Evaluate the performance of the final 3D Router (Area, Power, and Speed)

3. Write a thesis

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Design & Simulation Approach†

Fig.1 Design & Simulation Approach

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Research Plan†

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Step 1†

Understand the following:

Yuuki Tanaka, Architecture and Design of an Efficient Router for OASIS 3D Network-on-Chip System, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2015.

Option:

What is OASIS NoC? Slides 1; Slides 2
Thesis.pdf,

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Step 2†

Understand OASIS 3D-Router Verliog HDL Source Code

Run on your machine these 2 tutorials (IN ORDER):

OASIS 3D Router Design Tutorial, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, July 8, 2014.

How to Login and use VDEC tools on zxp035? --> Go to this page

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References†

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Verilog Code†

3D OASIS NoC Verilog HDL Code

Updates: