NASH FPGA Prototyping の履歴(No.13) - ASL Wiki

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NASH:Neuro-inspired ArchitectureS in Hardware

Group Meeting Schedule

May 27, 2019
June 10, 2019, 4 PM
June 24, 2019, 4PM
July 11, 2019, 4PM

Members†

Vu
Mark
Dang (Project Manager)
Ben

NASH Hardware Specificaiton†

Vu-kun, pelase add description here

NASH Hardward Design†

Before you intent to edit Verilog source code, please carefully check this guideline: Verilog Guideline

SNPC tile architectre and design with onchip learning†

SNPC architecture with SRAM†

verilog code , slides+waveform

SNPC Hardware Design and simulation
- Leader: Mark (please upalod your design report here)

Converting MNIST to Spike†

Mathab code, slides

SNPC architecture with Xbar†

to be completed

SNPC Architecture with Learning (STDP) and SRAM/Xbar†

Current state

Refrence†

Encoding Analog Input Data into Spike Trains†

Using either a rate based method, some form of temporal coding, or population coding reference

Python code
Verilog code

OASIS Reference†

OASIS 2D Router (sourcecode)
OASIS 3D Router (sourcecode)
NI
MC Router (sourcecode)
LIF Core (sourcecode)
OASIS Routers Hardware Design Tutorials