Available Research Topics の履歴(No.13) - ASL Wiki

[ トップ ] [ 新規 | 一覧 | 検索 | 最終更新 | ヘルプ ]

PHENIC:Si-Photonics Netwok-on-Chip†

==> Go to PHENIC Project Page

References:

Read this document first (.pdf)

Introduction To Network Simulation With OMNET++: A case of PhoenixSim. (PDF)
PhoenixSim 1.0 source files
PhoenixSim 1.0 user manual
Hybrid Photonic NoC based on Non-blocking Photonic Switch and Light-weight Electronic Router.

References:

Ryuya Okada, Architecture and Design of Core Network Interface for Distributed Routing in OASIS NoC, Slides, Technical Report

Achraf Ben Ahmed, Akram Ben Ahmed, A. Ben Abdallah, Novel Si-Photonics Network-on-Chip for Future Generations of Many-core Systems-on-Chip, submitted to (Journal of Parallel and Distributed Computing)(PDF),(Latex).

Achraf Ben Ahmed, Akram Ben Ahmed, Y.Okuyama, A. Ben Abdallah, Low-overhead Path-setup Algorithm for Energy-efficient Hybrid Silicon-Photonic Network-on-Chip Systems, submitted to The IEEE 7th International Conference on Awareness Science and Technology (ICAST 2015) (PDF , Latex).

3. Design of High-speed Optical Router Architecture for PHENIC Many-core Systems†

References:

Hybrid Photonic NoC based on Non-blocking Photonic Switch and Light-weight Electronic Router.

OASIS NoC Project

Fault-tolerant Router for Highly-reliable Many-core 3D-NoC Systems, The 3rd International Scientific Conference on Engineering and Applied Sciences (ISCEAS 2015), July 29-31, 2015, Okinawa, Japan.

OASIS 3D-Router Hardware Physical Design, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, University of Aizu, July 8, 2014.

OASIS: Reliable Network-on-Chip †

==>go to OASIS Project Page

4. Design and Evaluation of 3D OASIS Router with Through-Silicon-Via (TSV)†

References:

OASIS 3D-Router Hardware Physical Design, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, July 8, 2014.

OASIS 3D Fault Tolerant Router Hardware Physical Design with TSV, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, May 28, 2015.

Processing Cores for Adaptive computing †

Adaptive Processor†

5. Implementation of task assignment algorithm†

Implementation of architecture (Ishikuro)†

Matrix Processor†

6. Layout design of Matrix-ALU†

Practical interface between host computer/routers (Nakamura)†

Embedded navigation system as a practical application (Yusuke)†

Advanced Vision Processing Algorithms†

Architecture exploration of 2DCDP for 3D-chips†

7. Video recognition with TSCDP (Hayamizu)†

Real Time Signal Processing†

Extraction of training efficiency from EEG (Ito)†

8. P300 detection from few electrodes†

Design and Evaluation of Efficient Error Detection Mechanism for OASIS 3D-NoC, B4 Mitsunari Ishii

Design and Evaluation of 3D-OASIS-NoC Matrix Processor,

Performance Study and Evaluation of OASIS Network-on-Chip on FPGA)