NASH FPGA Prototyping の履歴(No.12)

• 履歴一覧
• 差分 を表示
• 現在との差分 を表示
• ソース を表示
• NASH FPGA Prototyping へ行く。
  • 1 (2018-03-19 (月) 03:16:03)
  • 2 (2018-03-19 (月) 06:19:14)
  • 3 (2018-03-19 (月) 06:34:27)
  • 4 (2019-05-14 (火) 08:01:41)
  • 5 (2019-05-27 (月) 02:52:47)
  • 6 (2019-05-29 (水) 02:28:25)
  • 7 (2019-06-03 (月) 04:01:15)
  • 8 (2019-06-10 (月) 08:05:42)
  • 9 (2019-06-13 (木) 03:26:35)
  • 10 (2019-06-13 (木) 07:02:12)
  • 11 (2019-06-17 (月) 03:07:41)
  • 12 (2019-07-03 (水) 01:17:06)
  • 13 (2019-07-03 (水) 05:34:10)
  • 14 (2019-07-04 (木) 07:17:19)
  • 15 (2019-07-05 (金) 04:32:07)

• Group Meeting Schedule

• May 27, 2019
• June 10, 2019, 4 PM
• June 24, 2019, 4PM
• July 11, 2019, 4PM

Members†

• Vu
• Mark
• Dang (Project Manager)
• Ben

NASH Hardware Specificaiton†

• Vu-kun, pelase add description here

NASH Hardward Design†

SNPC tile architectre and design with onchip learning†

SNPC architecture with SRAM†

• verilog code , slides+waveform

• SNPC Hardware Design and simulation
  • Leader: Mark (please upalod your design report here)

Converting MNIST to Spike†

• Mathab code, slides

SNPC architecture with Xbar†

• to be completed

SNPC Architecture with Learning (STDP) and SRAM/Xbar†

• Current state

Refrence†

Encoding Analog Input Data into Spike Trains†

Using either a rate based method, some form of temporal coding, or population coding reference

• Python code
• Verilog code

OASIS Reference†

• OASIS 2D Router (sourcecode)
• OASIS 3D Router (sourcecode)
• NI
• MC Router (sourcecode)
• LIF Core (sourcecode)
• OASIS Routers Hardware Design Tutorials