On the Design of Adaptive Digital Neuromorphic System
Research on Fault-tolerant Spiking Neuromorphic System based on Packet Switched On-chip Network & On-chip Learning

NASH progress meetings

Research Background

As artificial neural networks (ANNs) are executed in a fully synchronized manner, most of the computation is inherently uselessly done. For instance, a visual-based ANN performing object tracking analyses the entire image at each timestamp while most of the information remains unchanged within small time intervals. Another consequence of the synchronous execution is that traditional ANNs are not optimized to extract the timing information. In contrast, neuromorphic systems are characterized by the asynchronous and independent execution of the neurons within the neural net, therefore enabling more flexibility, as well as the ability to learn the timing information. [www].

It has been understood that spiking neural networks (SNNs) and synaptic devices can achieve high energy efficiency and fault tolerance in complex tasks by emulating biological neurons and synapses. Hence, they have a big potential for the replacement of traditional von Neumann computers. [WWW.ref].

SNNs can achieve better power efficiency when more powerful encoding methods are applied, or when SNNs are optimized for short latency. Second, the inference results in SNNs can be gotten faster than ANNs, though the precision may be lower. The inference precision would then rise with more evidence accumulated over time Ref. Spiking neurons are only activated when sufficient signals are integrated from other neurons, therefore the neural activities at the network level are usually sparse, which can make executing SNNs by matrix-based operation on a traditional CPU or GPU inefficient.Ref.

One issue in SNNs is that the spike function is non-differentiable, making it impossible to use backpropagation to train the network. To address this issue, several solutions have been proposed, such as converting DNNs to SNNs, and approximating the derivative of the spike function [ref]

Neuromorphic hardware is designed to accelerate the running of SNNs by allocating spiking neurons and synapses to neuromorphic chips and it can increase the power efficiency of SNNs by event-based computing.

Research Goal

The goal of this Doctoral thesis is to research and implement a Deep Spiking Neural Network Architecture with on-chip learning scheme and based on the previously developed schemes NASH1

The expected outputs from this research are:

Research Schedule

DateTask
☑️April 1st 2019 - August 30, 2019Survey, etc.
☑️September 1st, 2019 - July 31,2020Complete SNPC on-chip learning with STDP
September 21, 2020JoS paper draft
☑️August 16, 2020 to September 21, 2020Understand and run demo of k-means clustering based fault-tolerant multicast spike routing algorithm
☑️August 16, 2020 to September 21, 2020Replace spike injector with SNPC and run again the demo of k-means clustering based fault-tolerant multicast spike routing algorithm
☑️September 1, 2020 to December 4, 2020Integrate SNPC into 3D-NoC architecture
☑️September 1, 2020 to February 28, 2021Prepare journal paper draft on the 3D-NoC SNN
☑️March 1, 2021 to March 3, 2021Prepare journal draft for MDPI Electronics
☑️March 3, 2021 to March 5, 2021Prepare conference draft for UNET21
☑️March 5, 2021 to March 21, 2021Prepare conference draft for Reversible Computing 13
☑️March 19, 2021 to March 24, 2021Update journal manuscript for MDPI Electronics
☑️April 2, 2021 to April 17, 2021NASH tutorial
☑️April 6, 2021 to April 9, 2021Desertation draft structure
May 18, 2021 to May 30, 2021Investigate more biological benchmarks on NASH, including Hand Gesture Recognition
☑️April 28, 2021 to May 6, 2021UNET Camera ready paper
☑️April 18, 2021 to May 21, 2021Dissertation draft completion preparation of documents for the Doctoral Dissertation Preliminary Review
☑️May 10, 2021Preparation of documents for the Doctoral Dissertation Preliminary Review
☑️June 7First Dissertation Preliminary Presentation Rehearsal
☑️June 14Second Dissertation Preliminary Presentation Rehearsal
July 1, 2021 to September 31, 2021Begin work on NeuroSys
☑️July 1, 2021 to July 12, 2021Complete initial exploration of RBTC application
☑️August 1, 2021 to August 7, 2021Survey on invasive and non-invasive prosthetics, investigate gesture recognition ANN implementation on Raspberry pi
August 8, 2021 to August 14, 2021Update prosthetics journal draft with Williams, Begin implementation of gesture recognition ANN on raspberry pi
August 15, 2021 to August 28, 2021Implementation of gesture recognition ANN on raspberry pi
September 1, 2021 to September 31, 2022Preparation of Dissertation Draft version 2, SNN implementatioin on raspberry pi
☑️August 26, 2021 to September 3, 2021Journal Paper first draft
January 3, 2021Completion of Final review slides
January 6, 2022Final review presentation rehearsal
December 13, 2021 to December 31, 2021Conference paper complete draft
Schedule last Updated on: 12/27/2021

Doctoral Dissertation Review Procedure (AY2022 Spring Ref)

DateTask
☑️March 22, 2021Submission of dissertation title and list of referees
☑️May 17, 2021Submission of the documents for the Doctoral Dissertation Preliminary Review
☑️June 18, 2021Doctoral dissertation Rreliminary Review
☑️December 17, 2021Submission of the documents for the Doctoral Dissertation final Review
January 12, 2022Doctoral Dissertation Final Review
January 24, 2022Committee Meeting
January 28, 2022Submission of the materials for the presentation
February 15, 2022Submission of finalized Dissertations and their abstracts
February 15, 2022Submission of the Abstracts of the Results Regarding the Final Doctoral Dissertation Review
February 15, 2022Submission of Consent to Use of Academic Paper / Repository Registration Request Form
February 15, 2022Submission of the Application Form for the Academic Degree
February 16, 2022Dissertation presentation
Schedule last Updated on: 12/21/2021

Doctoral Dissertation

Research Progress - ===> previous tasks

Ongoing Papers

65k-Synapse 256-Neuron Online-Learning Spiking Neuron-Processing Core for Digital 3D-NoC-based Neuromorphic Processor

Tutorials

Achievement

Published papers

Three Dimensional NoC-based Digital Neuromorphic System with On-chip Learning

On the Design of a Fault-tolerant Scalable Three Dimensional NoC-based Digital Neuromorphic System with On-chip Learning

Design and Evaluation of SNPC for (IEEE_BigCom2020) conference. Full paper submisison due date: Sept 30, 2019

The ACM Chapter International Conference on Educational Technology, Language and Technical Communication (ETLTC). Full paper submisison due date: Nov. 19, 2019

UoA Research Progress Seminar

Preliminary Theis

Final Thesis

My Shared Google Drive Folder

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