![[PukiWiki]](image/pukiwiki.png "[PukiWiki]")
The main goal of this project is to research about algorithms and, architecture for a Reliable Many-core 3D-NoC System Targeted for Real-Time Vision Applications (i.e., gesture/motion/object recognition/surveillance). The system is based on our earlier developed reliable Network-on-Chip (OASIS). The system will integrate several dedicated PEs for ILP/Data/Thread level parallelism, while the 3D-OASIS NoC orchestrates communications between PEs and is used for large amount of data transactions among tasks.
Sub-project title: Hardware Implementation of Real-Time Low-level Vision Processing Algorithms
Vision algorithms play a very important role in vision processing, and it is widely applied in many aspects such as medical care, surveillance, traffic management, etc. Most of the situations require the process to be real-timed, in other words, as fast as possible.
FPGAs have the advantage of parallelism fabric in programming, comparing to the serial communications of CPUs, which makes FPGA a perfect platform for implementing vision algorithms.
These algorithms usually have a very high computation power because the objects, which is a large amount of pixels of a single picture, have to be proceeded not once, but many times.
The goal of this project is to study low-level vision processing algorithms on FPGA. Bellow are our available research topics for GT 2015:
Update: Dec. 1, 2014 - B.
