OASIS の履歴(No.11)

OASIS Network-on-Chip Project

Project Description:†

Future embedded and general purpose processor architectures will be implemented as multicore systems with nanoscale technology consisting of hundreds of processing and storage elements. These multicore systems are emerging as a key design solution for today's nanoelectronics design problems. The interconnection structure supporting such systems will be closer to a sophisticated network than to current bus-based solutions. Such network must provide high throughput and low latency while keeping area and power consumption low.

Our research efforts is about solving several design challenges to enable such new paradigm in Multicore Systems. In particular, we are investigating implementation techniques for basic building blocks, new topologies, flow control techniques, and low-latency, high-throughput/fault-tolerant routing algorithms.

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Members†

D3 Akram

Former Members:

Endou
Uesaka
Mori
Miura

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Group Publications†

Akram Ben Ahmed, A. Ben Abdallah, Graceful Deadlock-Free Fault-Tolerant Routing Algorithm for 3D Network-on-Chip Architectures, Journal of Parallel and Distributed Computing, 2014. [DOI]

Akram Ben Ahmed, Achraf Ben Ahmed, A. Ben Abdallah, Deadlock-Recovery Support for Fault-tolerant Routing Algorithms in 3D-NoC Architectures, IEEE Proceedings of the 7th International Symposium on Embedded Multicore/Many-core SoCs (MCSoC-13), pp., 2013. [DOI]

Akram Ben Ahmed, A. Ben Abdallah, Architecture and Design of High-throughput, Low-latency and Fault Tolerant Routing Algorithm for 3D-Network-on-Chip, The Jnl. of Supercomputing, December 2013, Volume 66, Issue 3, pp 1507-1532. [DOI]

Akram Ben Ahmed, T. Ouchi, S. Miura, A. Ben Abdallah, Run-Time Monitoring Mechanism for Efficient Design of Application-specific NoC Architectures in Multi/Manycore Era, IEEE Proc. of the 6th International Workshop on Engineering Parallel and Multicore Systems (ePaMuS2013'), July 2013. [DOI]

Akram Ben Ahmed, T. Ouchi, S. Miura, A. Ben Abdallah, Run-Time Monitoring Mechanism for Efficient Design of Application-specific NoC Architectures in Multi/Manycore Era, Proc. IEEE 6th International Workshop on Engineering Parallel and Multicore Systems (ePaMuS2013'), July 2013.

Akram Ben Ahmed, A. Ben Abdallah, Low-overhead Routing Algorithm for 3D Network-on-Chip, IEEE Proc. of the The Third International Conference on Networking and Computing (ICNC'12), pp. 23-32, 2012. [DOI]

Akram Ben Ahmed, A. Ben Abdallah, LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture, '''IEEE Proceedings of the 6th International Symposium on Embedded Multicore SoCs (MCSoC-12), pp. 167-174, 2012. [DOI]

Akram Ben Ahmed, A. Ben Abdallah, ONoC-SPL Customized Network-on-Chip (NoC) Architecture and Prototyping for Data-intensive Computation Applications, '''IEEE Proceedings of The 4th International Conference on Awareness Science and Technology, pp. 257-262, 2012. DOI

Kenichi Mori,A. Ben Abdallah, OASIS Network-on-Chip Prototyping on FPGA, Master's Thesis, The University of Aizu, Feb. 2012. [Thesis], [slides]

Ben Ahmed Akram, A. Ben Abdallah,[[On the Design of a 3D Network-on-Chip for Many-core SoC, Master's Thesis, The University of Aizu, Feb. 2012. [Thesis], [slides]

Shohei Miura, A. Ben Abdallah, Design of Parametrizable Network-on-Chip, Master's Thesis, The University of Aizu, Feb. 2012.

R. Okada, Architecture and Design of Core Network Interface for Distributed Routing in OASIS NoC, Technical Report, ASL- Parallel Architecture Group, School of Computer Science and Engineering, The University of Aizu, March 2012.

A. Ben Ahmed, A. Ben Abdallah, K. Kuroda,Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC, IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), pp.67-73, Nov. 2010. (best paper award) (Slides), (Papers)

K. Mori, A. Esch, A. Ben Abdallah, K. Kuroda, Advanced Design Issues for OASIS Network-on-Chip Architecture, IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010),pp.74-79, Nov. 2010. (Slides); (Paper)

SLIDE

Shohei Miura, Abderazek Ben Abdallah, Kenichi Kuroda, PNoC: Design and Preliminary Evaluation of a Parameterizable NoC for MCSoC Generation and Design Space Exploration, The 19th Intelligent System Symposium (FAN 2009), pp.314-317, Sep.2009. SLIDE

Kenichi Mori, Abderazek Ben Abdallah, Kenichi Kuroda, Design and Evaluation of a Complexity Effective Network-on-Chip Architecture on FPGA, The 19th Intelligent System Symposium (FAN 2009), pp.318-321, Sep. 2009. SLIDE

A. Ben Abdallah, T. Yoshinaga and M. Sowa, "Mathematical Model for Multiobjective Synthesis of NoC Architectures", IEEE Proc. of the 36th International Conference on Parallel Processing, Sept. 4-8, 2007. (PDF)

A. Ben Abdallah, Masahiro Sowa, "Basic Network-on-Chip Interconnection for Future Gigascale MCSoCs Applications: Communication and Computation Orthogonalization", JASSST2006, Dec. 4-9th, 2006. (PDF)

T. Uesaka, OASIS NoC Topology Optimization with Short-Path Link, Technical Report, Systems Architecture Group,March 2011.PDF

K. Mori, A. Ben Abdallah, OASIS NoC Architecture Design in Verilog HDL, Technical Report,TR-062010-OASIS, Adaptive Systems Laboratory, the University of Aizu, June 2010. PDF

Theses:

Shuu Endou, Hardware Prototyping and Evaluation of Distributed Routing Core Network-Interface for OASIS NoC Architecture, Bachelor Thesis, School of Computer Science and Engineering,The University of Aizu, Feb. 2013 (slides)

Ryuya Okada,A. Ben Abdallah,Architecture and Design of Core Network Interface for Distributed Routing in OASIS NoC, Graduation Thesis, The University of Aizu, Feb. 2012. slides, Technical Report

Kenichi Mori,A. Ben Abdallah, OASIS Network-on-Chip Prototyping on FPGA, Master's Thesis, The University of Aizu, Feb. 2012.slides, technical report

Ben Ahmed Akram, A. Ben Abdallah,On the Design of a 3D Network-on-Chip for Many-core SoC , Master's Thesis, The University of Aizu, Feb. 2012. slides

Shohei Miura,A. Ben Abdallah,Efficient Design Method for NoC using Monitoring Mechanism:Parameterziable Network-on-Chip Master's Thesis, The University of Aizu, Feb. 2012. slides, technical report

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Technical Reports and Tutorials†

OASIS 3D-Router Physical Design: I of III, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, June 5, 2014.