Available Research Topics の履歴(No.11)

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PHENIC:Si-Photonics Netwok-on-Chip†

• References:

• Introduction To Network Simulation With OMNET++: A case of PhoenixSim. (PDF)
• PhoenixSim 1.0 source files
• PhoenixSim 1.0 user manual

• References:

• Achraf Ben Ahmed, Akram Ben Ahmed, A. Ben Abdallah, Novel Si-Photonics Network-on-Chip for Future Generations of Many-core Systems-on-Chip, submitted to (Journal of Parallel and Distributed Computing)(PDF),(Latex).

• Achraf Ben Ahmed, Akram Ben Ahmed, Y.Okuyama, A. Ben Abdallah, Low-overhead Path-setup Algorithm for Energy-efficient Hybrid Silicon-Photonic Network-on-Chip Systems, submitted to The IEEE 7th International Conference on Awareness Science and Technology (ICAST 2015) (PDF , Latex).

Design of High-speed Optical Router Architecture for PHENIC Many-core Systems†

• References:

• OASIS NoC Project

• Abderazek Ben Abdallah, Mitsuhiro Nakamura, Akram Ben Ahmed, Yuichi Okuyama, Fault-tolerant Router for Highly-reliable Many-core 3D-NoC Systems, The 3rd International Scientific Conference on Engineering and Applied Sciences (ISCEAS 2015), July 29-31, 2015, Okinawa, Japan.

• Akram Ben Ahmed, OASIS 3D-Router Hardware Physical Design, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, University of Aizu, July 8, 2014.

OASIS: Reliable Network-on-Chip †

Design and Evaluation of 3D OASIS Router with Through-Silicon-Via (TSV)†

Processing Cores for Adaptive computing †

• Adaptive Processor
  • Implementation of task assignment algorithm
  • Implementation of architecture (Ishikuro)
• Matrix Processor
  • Layout design of Matrix-ALU
  • Practical interface between host computer/routers (Nakamura)
  • Embedded navigation system as a practical application (Yusuke)

Advanced Vision Processing Algorithms†

• Architecture exploration of 2DCDP for 3D-chips
• Video recognition with TSCDP (Hayamizu)

Real Time Signal Processing†

• Extraction of training efficiency from EEG (Ito)
• P300 detection from few electrodes

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Previous Topics†

• Design and Evaluation of Efficient Error Detection Mechanism for OASIS 3D-NoC, B4 Mitsunari Ishii (COMPLETED)

• Design and Evaluation of 3D-OASIS-NoC Matrix Processor,