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Electronic packet-switched on chip interconnects alleviate the problems of poor scalability, limited bandwidth, and high power consumption in traditional designs. This interconnection paradigm when combined with 3D integration technology offers advantages over 2D NoC design, such as shorter wire length, higher packing density, and smaller footprint. However, as feature sizes continue to shrink and as we are heading towards complex and large system design consisting of hundreds of PEs, traditional design approaches may not be enough for providing significant large bandwidth with low-power consumption. Optical Network-on-Chip (ONoC) promises significant advantages over their electronic counterparts. In particular, they offer a potentially disruptive technology solution with fundamentally low power dissipation that remains independent of capacity while providing ultra-high throughput and minimal access latency. In this project, we research about the development of a high-performance and low-power on-chip silicon pohotonic NoC for heterogeneous complex many-core systems. Our approach is an extension of our earlier OASIS 3D-ENoC and off ers low-latency data propagation and ultra-wide bandwidth by leveraging wavelength-division multiplexing and time-division multiplexing. We also focus on the development of efficient routing, and thermal power optimizations algorithms.
The cores within PHENIC processor can communicate almost instantaneously due to the low latency and high bandwidth characteristics of optical communications. This will improve performance, power/energy efficiency and the programmability of the PHENIC chip.
PHENIC Poster "PDF"