OASIS-8C: Verilog Design and FPGA Prototyping of 8-core OASIS Network-on-Chip System
Project Goal†
- Real design in verilog HDL and prototyping on FPGA of a small scale 8-core OASIS Network-on-Chip System.
- Detailed Design Manual.
Members†
System Architecture†
Specification†
- System specifications:
- OASIS 3D Network-on-Chip [Ref.1].
- Topology: 3D Mesh.
- Network's Size: 2x2x2.
- Document & source code: [Ref.1]
- Network Interface: [Ref.2].
- Processing Elements:
- CPU: MIPS
- MEM: On-chip (verilog code), Off-chip (see I/O).
- I/O: Off-chip Memory, Display (LCD, LED), Inter-connection (UART/USB/PCI).
- Application specifications:
- Target CPU: MIPS.
- Target applications: TBD.
- Implementation environment:
- Language: Verilog HDL.
- Simulation tool: Modelsim Altera/Cadence Tools.
- Implementation tool: Altera Quartus II/ASIC.
- Implementation board: Spartan DE II/CMOS 45 nm.
- Resource:
- Logic:
- Register:
- I/O:
- External devices:
- Note:
Hardware Prototyping Phases†
- Step 01: Design Preparation.
- Decide the system's specification.
- Prepare the required tools, boards and source code.
- Step 02: Individual Network Tile (PE-NI-R) Implementation.
- Establish an individual network tile: PE(Processing Element) - NI(Network Interface) - R(Router).
- I/O Interface connection.
- Connection synchronization.
- Demo application implementation on FPGA/ASIC.
- Step 03: 2D 2x2 Network Implementation.
- Establish a 2D 2x2 Network Implementation (2 CPUs, 1 Memory, 1 I/O).
- Demo application implementation on FPGA/ASIC.
- Step 04: 3D 2x2x2 Network Implementation.
- Establish the proposal architecture.
- Demo application implementation on FPGA/ASIC.
Schedule†
- Detail of schedule
| Step | Content | Start Date | Finish Date | Report |
| 1 | Design Preparation | 2015-June-02 | 2015-June-19 | this page |
| 2 | An Individual Network Tile | 2015-July-01 | 2015-Sep-30 | link |
| 3 | A 2D (2x2) Network | 2015-Oct-01 | 2015-Dec-15 | link |
| 4 | A Full (2x2x2) System | 2015-Dec-16 | 2016-02-15 | link |
- Task Assignment (Step 02)
| No. | Assignee | Task | Finish Date | Note |
| 1 | Khanh | Prepare the schedule of the Project | 2015-Jun-19 | - |
| 2.1 | All | 3D NoC Simulation | 2015-XX-YY | - |
| Kajikawa | -- | -- | -- |
| Yatsu | -- | -- | -- |
| Miyamoto | -- | -- | -- |
| Khanh | Prepare the schedule, source code of 2x2x2 | -- | -- |
| 2.2 | All | Network Tile Synchronization | 2015-XX-YY | - |
| 2.3 | All | Program Demonstration | 2015-XX-YY | - |
| 2.4 | All | Tile Implementation | 2015-XX-YY | - |
References†
Last Update:
- 2015 June 8th: Update system architecture diagram.
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