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A presentation of individual research progress
Date Presenters Notes April 10 Masuda,Hoshino April 17 Maekawa,Masuda April 24 Hoshino, Maekawa May 1 Haga,Reo,Mori,Miura May 8 Hoshino,Maekawa,Masuda Absent: Reo May 15 Haga,Reo,Mori,Miura Absent: Reo May 22 Hoshino,Maekawa,Masuda Absent: Masuda, Mori May 29 Haga,Reo,Mori,Miura June 5 Haga,Reo,Mori,Miura,Masuda June 12 Haga,Reo,Mori,Miura,Maekawa June 19 Haga,Reo,Mori,Miura,Hoshino June 26 Haga,Reo,Mori,Miura,Masuda
Journals papers and conferences:
- The QC-2 Parallel Queue Processor Architecture, Journal of Parallel and Distributed Computing, Vol. 68, No. 2, (2008), pp. 235– 245.
- Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core", International Conference on Embedded and Ubiquitous Computing (EUC2005), LNCS Vol.3824, pp. 340-349, 2005 |PDF|SLIDES|
- Queue Processor for Novel Queue Computing Paradigm Based on Produced Order Scheme, IEEE computer Society, Proc. of the The 7th High Perfomance Computing and Grid in Asia Pacific Region (HPCAsia2004), pp. 169-177, July 2004.
Techinical Reports:
- QueueCore - The Strong Wave!, Technical report, Ref: QC2MY07BAA, May 2007
- QC-1 Processing Stages Algorithms,Technical Report, Ref: TRQC1PSA03, UEC, IS, October
- QueueCore Instruction Set Architecture,Technical Report, Jan. 2003-2005.
- QueueCore Data Path (earlier version), Technical Report, IS, UEC,Oct., 2002.
