Vu Huy The の履歴(No.1)

NASH: Neuro-inspired ArchitectureS in Hardware Project

Doctoral Topic: Adaptive Neurochip for Spiking Deep Neural Networks with Scalable Packet-Switched Network

Background - Multicore neuromorphic architectures†

The biological brain implements massively parallel computations using a complex architecture that is different from current Von Neuman machine. Our brain is a low-power, fault-tolerant and high-performance machine! It consumes only about 20W and brain circuits continue to operate as the organism needs even when the circuit (neuron, neuroglia, etc.) is perturbed or died.

Conventional neural networks encode information with static input coding, eg. encoding a pattern as 0011 (binary bits) for 4 input neurons, and another pattern 0010. While in SNN, besides the pattern code, the time-related factors, eg. spiking rate, spiking rank and spiking intervals, can be used to present the information. This greatly increases the information processing capacity of a neural network.

SNN only process information when spikes occur. As a result, SNNs consume almost no energy when no spikes occur [www]. A biological SNN (e.g. mammalian brains) uses a spike rate of only several KHz to finish a complex task (e.g. vision pattern recognition) with each spike consumes an energy of in fJ per synapse.

Spiking neural network (SNN) simulations are a flexible and powerful method for investigating the behavior of neuronal systems. However, simulation of the spiking neural networks in software is slow. An alternative approach is a hardware implementation of such system, which provides the possibility to generate independent spikes accurately and simultaneously output spikes in real time. Also, the spiking neural network can take full advantage of hardware inherent parallelism. SNN and ANN are widely used in signal processing, speech synthesis, pattern recognition, and so forth.

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Project Goal†

Implementing an SNN or a Deep Neural Network (DNN) in embedded systems is a challenging task, because a typical DNN, such as the Deep Belief Network using 128x128 images as input, could exhaust Giga bytes of memory and result in bandwidth and computation bottleneck.

To solve these implementation issues, a new efficient architecture is required based on a packet-switched network will be developed. NoC is introduced to solve the existing problems in SNN/ANN, such as heavy communication load and lack of reconfigurability. In the proposed system, the weight values and activation functions can be reconfigured (or adaptively reduces the weights) as desired. Also, the topology and routing algorithm of the NoC can be changed by sending new data (packets) to satisfies different kinds of SNN.

The goal of this research is to develop an efficinet adaptive spiking neuro-inpired architecture in hardware. In paticular, the research consisits of:

(1) An efficient adaptive configuration method which enable reconfiguration of different SNN parameters (spike weights, routing, hidden layers, topology, etc.)
- A neuron with a programmable threshold and an accumulate and fire charge function.
- A synapse with a programmable weight, distance, and refractory period.
- A fan-in/fan-out element to expand or increase the connectivity of elements beyond their nearest neighbors.

(2) A mixture of different topologies/Architecture (Feedforward and Recurrent) will be investigated

(3) Efficient on-chip learning Algorithm

(4) Performance evaluation and comparisons against existing HW and SW solutions.

To demonstrate the performance of the algorithms and the system, an FPGA implementation shall be developed and interfaced to a small drone. In addition, a VLSI implementation of the Adaptive (different applications and learning) spiking OASIS-NP shall be also developed.

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Research schedule†

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Oct. to Feb. 2017 †

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Step 5 Due date: March 10, 2017†

Step 5.1 Propose a Low-power, Light-weight Learning Circuit/Algorithm for NASH System. (NASH stands for 'Neuro-inspired ArchitectureS in Hardware' Project in ASL)