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The biological brain implements massively parallel computations using a complex architecture that is different from current Von Neumann machine. Our brain is a low-power, fault-tolerant and high-performance machine! It consumes only about 20W and brain circuits continue to operate as the organism needs even when the circuit (neuron, neuroglia, etc.) is perturbed or died. Our goal in this project is to research and develop in hardware an adaptive low-power and reliable neuro-inspired manycore SoC with on-chip learning and cognitive capabilities targeted for pattern recognition and complex cognitive tasks. Our other goal is to investigate and develop a low-power and low-cost platform for running large-scale simulations of biological brains in real-time targeted for neuroscience applications. Currently, we are investigating the following problems: the communication network for neuro-inspired chips, reconfigurability and adaptability methods, fault-tolerance, and learning circuits. In addition to these two target applications, lessons learned from this project will be also used to optimize power & performance of the conventional architectures.
