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@Conference{Abdallah2015Fault,
Title = {Fault-tolerant Router for Highly-reliable Many-core 3D-NoC Systems},
Author = {A. Ben Abdallah and M. Nakamura and Akram Ben Ahmed and M. Meyer and Y. Okuyama},
Booktitle = {The 3rd International Scientific Conference on Engineering and Applied Sciences (ISCEAS 2015)},
Year = {2015},
Owner = {Khanh},
Timestamp = {2015.05.31},
Url = {http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/ISCEAS2015/ISCEAS2015_Manuscript.pdf}
}
@InProceedings{Ben2006BNI,
Title = {{Basic Network-on-Chip Interconnection for Future Gigascale MCSoCs Applications: Communication and Computation Orthogonalization}},
Author = {A. Ben Abdallah and Masahiro Sowa},
Booktitle = {JASSST2006},
Year = {2006},
Owner = {Khanh},
Timestamp = {2014.11.11}
}
@InProceedings{Ben2007MMf,
Title = {{Mathematical Model for Multiobjective Synthesis of NoC Architectures}},
Author = {A. Ben Abdallah and T. Yoshinaga and M. Sowa},
Booktitle = {IEEE Proc. of the 36th International Conference on Parallel Processing},
Year = {2007},
Owner = {Khanh},
Timestamp = {2014.11.11}
}
@InProceedings{Akram2012LRA,
Title = {{Low-overhead Routing Algorithm for 3D Network-on-Chip}},
Author = {Ahmed, A.B. and Abdallah, A.B.},
Booktitle = {Networking and Computing (ICNC), 2012 Third International Conference on},
Year = {2012},
Month = {Dec},
Pages = {23-32},
Doi = {10.1109/ICNC.2012.14},
Keywords = {field programmable gate arrays;logic design;network routing;network-on-chip;system-on-chip;2D-NoC;3D-NoC designs;3D-NoC routing algorithm;3D-OASIS-NoC;FPGA;RPM routing algorithms;SoC;hardware complexity;look-ahead-XYZ;low-overhead routing algorithm;power consumption;randomized partially minimal routing algorithms;shared-bus based systems;systems-on-chip;third dimension network-on-chip;transpose traffic pattern;Algorithm design and analysis;Computer architecture;Pipelines;Ports (Computers);Routing;Switches;Throughput;3D NoC;Architecture;Concurrent;Look-Ahead Routing}
}
@PhdThesis{Ahmed2015High,
Title = {High-throughput Architecture and Routing Algorithms Towards the Design of Reliable Mesh-based Many-Core Network-on-Chip Systems},
Author = {Akram Ben Ahmed},
School = {Graduate School of Computer Science and Engineering, University of Aizu},
Year = {2015},
Month = {March},
Owner = {Khanh},
Timestamp = {2015.05.31},
Url = {http://web-ext.u-aizu.ac.jp/~benab/publications/theses/Akram-PhD-15/AkramBenAhmed_Thesis_2015.pdf}
}
@MastersThesis{Akram2012OtD,
Title = {{On the Design of a 3D Network-on-Chip for Many-core SoC, Master's Thesis}},
Author = {Akram Ben Ahmed},
School = {The University of Aizu},
Year = {2012},
Month = {Feb.},
Owner = {Khanh},
Timestamp = {2014.11.11}
}
@TechReport{Akram2014O3H,
Title = {{OASIS 3D-Router Hardware Physical Design}},
Author = {A. Ben Ahmed and A. Ben Abdallah},
Institution = {Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu},
Year = {2014},
Owner = {Khanh},
Timestamp = {2014.11.08}
}
@Article{Akram2013Aad,
Title = {{Architecture and design of high-throughput, low-latency, and fault-tolerant routing algorithm for 3D-network-on-chip (3D-NoC)}},
Author = {Ahmed, Akram Ben and Abdallah, Abderazek Ben},
Journal = {The Journal of Supercomputing},
Year = {2013},
Number = {3},
Pages = {1507--1532},
Volume = {66},
Owner = {Khanh},
Publisher = {Springer US},
Timestamp = {2014.10.17}
}
@InProceedings{Akram2012lll,
Title = {{LA-XYZ: low latency, high throughput look-ahead routing algorithm for 3D network-on-chip (3D-NoC) architecture}},
Author = {Ahmed, A Ben and Abdallah, A Ben},
Booktitle = {Embedded Multicore Socs (MCSoC), 2012 IEEE 6th International Symposium on},
Year = {2012},
Organization = {IEEE},
Pages = {167--174},
Owner = {Khanh},
Timestamp = {2014.10.22}
}
@InProceedings{Akram2013DRS,
Title = {{Deadlock-Recovery Support for Fault-tolerant Routing Algorithms in 3D-NoC Architectures}},
Author = {Ahmed, Akram Ben and Ahmed, Achraf Ben and Abdallah, Abderazek Ben},
Booktitle = {Embedded Multicore Socs (MCSoC), 2013 IEEE 7th International Symposium on},
Year = {2013},
Organization = {IEEE},
Pages = {67--72}
}
@Conference{Akram2014AET,
Title = {{Adaptive Error-and Traffic-aware Router Architecture for 3D Network-on-Chip Systems}},
Author = {Ahmed, Akram Ben and Meyer, Michael and Okuyama, Yuichi and Abdallah, Abderazek Ben},
Booktitle = {IEEE Proceedings of the 8th International Symposium on Embedded Multicore/Many-core SoCs (MCSoC-14)},
Year = {2014},
Pages = {197--2014},
Doi = {10.1109/MCSoC.2014.36}
}
@TechReport{Ahmed2015OASIS,
Title = {OASIS 3D Fault Tolerant Router Hardware Physical Design with TSV},
Author = {Akram Ben Ahmed and Mitsuhiro Nakamura and Abderazek Ben Abdallah},
Institution = {University of Aizu},
Year = {2015},
Month = {May},
Owner = {Khanh},
Timestamp = {2015.05.31},
Url = {http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS-3DFTRV1_Design_Tutorial_05282015.pdf}
}
@Article{Akram2014gdf,
Title = {{Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures}},
Author = {Ben Ahmed, Akram and Ben Abdallah, Abderazek},
Journal = {Journal of Parallel and Distributed Computing},
Year = {2014},
Number = {4},
Pages = {2229--2240},
Volume = {74},
Abstract = {Three-Dimensional Networks-on-Chip (3D-NoC) has been presented as an auspicious solution merging the high parallelism of Network-on-Chip (NoC) interconnect paradigm with the high-performance and lower interconnect-power of 3-dimensional integration circuits. However, 3D-NoC systems are exposed to a variety of manufacturing and design factors making them vulnerable to dierent faults that cause corrupted message transfer or even catastrophic system failures. Therefore, a 3D-NoC system should be fault-tolerant to transient malfunctions or permanent physical damages.
In this paper, we present an ecient fault-tolerant routing algorithm, called Hybrid-Look-Ahead-Fault-Tolerant (HLAFT), which takes advantage of both local and look-ahead routing to boost the performance of 3D-NoC systems while ensuring fault-tolerance. A deadlock-recovery technique associated with HLAFT, named Random-Access-Buffer (RAB), is also presented. RAB takes advantage of look-ahead routing to detect and remove deadlock with no considerably additional hardware complexity. We implemented the proposed algorithm[1] and deadlock-recovery technique on a real 3D-NoC architecture (3D-OASIS-NoC[1]) and prototyped it on FPGA. Evaluation results show that the proposed algorithm performs better than XYZ, even when considering high fault-rates (i.e., 20%), and outperforms our previously designed Look-Ahead-Fault-Tolerant routing (LAFT) demonstrated in latency/flit reduction that can reach 12.5% and a throughput enhancement reaching 11.8% in addition to 7.2% dynamic-power saving thanks to the Power-management module integrated with HLAFT.},
Doi = {10.1016/j.jpdc.2014.01.002},
Owner = {Khanh},
Publisher = {Academic Press},
Timestamp = {2014.10.17},
Url = {http://web-ext.u-aizu.ac.jp/~benab/publications/journals/JPDC14/JPDC-preprint.pdf}
}
@InProceedings{Akram2010aad,
Title = {{Architecture and design of efficient 3D network-on-chip (3D NoC) for custom multicore SoC}},
Author = {Ben Ahmed, A and Ben Abdallah, A and Kuroda, Kenichi},
Booktitle = {Broadband, Wireless Computing, Communication and Applications (BWCCA), 2010 International Conference on},
Year = {2010},
Organization = {IEEE},
Pages = {67--73},
Owner = {Khanh},
Timestamp = {2014.10.22}
}
@InProceedings{Akram2013RMM,
Title = {{Run-Time Monitoring Mechanism for Efficient Design of Application-Specific NoC Architectures in Multi/Manycore Era}},
Author = {Ben Ahmed, A. and Ochi, T. and Miura, S. and Ben Abdallah, A.},
Booktitle = {Complex, Intelligent, and Software Intensive Systems (CISIS), 2013 Seventh International Conference on},
Year = {2013},
Month = {July},
Pages = {440-445},
Doi = {10.1109/CISIS.2013.80},
Keywords = {buffer storage;integrated circuit design;multiprocessing systems;multiprocessor interconnection networks;network-on-chip;system monitoring;PNoC;RMM;application-specific NoC architecture;architectural parameter;design decision;execution time;manycore era;multicore era;network-on-chip interconnect;optimal architecture hardware parameter;optimal buffers size;power consumption;power-hungry components;run-time monitoring mechanism;run-time traffic information;software simulation;storage buffer;system behavior;system performance;system resources;theoretical modeling;traffic flow monitoring;Algorithm design and analysis;Computer architecture;Hardware;Monitoring;Network-on-chip;Probes;Registers;Buffer Design;Design Method;NoC;Power-Reduction;Run-Time Monitoring}
}
@MastersThesis{Endou2013Hardware,
Title = {{Hardware Prototyping and Evaluation of Distributed Routing Core Network-Interface for OASIS NoC Architecture}},
Author = {Shuu Endou},
School = {The University of Aizu},
Year = {2013},
Month = {February},
Journal = {Bachelor Thesis, School of Computer Science and Engineering,The University of Aizu},
Owner = {Khanh},
Timestamp = {2014.11.11}
}
@MastersThesis{Muira2012DoP,
Title = {{Design of Parametrizable Network-on-Chip}},
Author = {Shohei Miura},
School = {The University of Aizu},
Year = {2012},
Month = {Feb.},
Owner = {Khanh},
Timestamp = {2014.11.11}
}
@InProceedings{Miura2009PDa,
Title = {{PNoC: Design and Preliminary Evaluation of a Parameterizable NoC for MCSoC Generation and Design Space Exploration}},
Author = {Shohei Miura and Abderazek Ben Abdallah and Kenichi Kuroda},
Booktitle = {The 19th Intelligent System Symposium (FAN 2009)},
Year = {2009},
Pages = {314-317},
Owner = {Khanh},
Timestamp = {2014.11.11}
}
@MastersThesis{Mori2012ONP,
Title = {{OASIS Network-on-Chip Prototyping on FPGA}},
Author = {Kenichi Mori},
School = {The University of Aizu},
Year = {2012},
Month = {Feb.},
Owner = {Khanh},
Timestamp = {2014.11.11}
}
@TechReport{Mori2010ONA,
Title = {{OASIS NoC Architecture Design in Verilog HDL}},
Author = {K. Mori and A. Ben Abdallah},
Institution = {Adaptive Systems Laboratory, the University of Aizu},
Year = {2010},
Month = {June},
Owner = {Khanh},
Timestamp = {2014.11.11}
}
@InProceedings{Mori2009dae,
Title = {{Design and evaluation of a complexity effective network-on-chip architecture on FPGA}},
Author = {Mori, Kenichi and Abdallah, A Ben and Kuroda, Kenichi},
Booktitle = {Proc. of The 19th Intelligent System Symposium (FAN 2009)},
Year = {2009},
Pages = {318--321},
Owner = {Khanh},
Timestamp = {2014.10.22}
}
@InProceedings{Mori2010Adi,
Title = {{Advanced design issues for OASIS network-on-chip architecture}},
Author = {Mori, Kenichi and Esch, Adam and Abdallah, A Ben and Kuroda, Kenichi},
Booktitle = {Broadband, Wireless Computing, Communication and Applications (BWCCA), 2010 International Conference on},
Year = {2010},
Organization = {IEEE},
Pages = {74--79}
}
@TechReport{Okada2012AaD,
Title = {{Architecture and Design of Core Network Interface for Distributed Routing in OASIS NoC}},
Author = {R. Okada},
Institution = {ASL- Parallel Architecture Group, School of Computer Science and Engineering, The University of Aizu},
Year = {2012},
Month = {March},
Owner = {Khanh},
Timestamp = {2014.11.11}
}
@MastersThesis{Okada2012Architecture,
Title = {{Architecture and Design of Core Network Interface for Distributed Routing in OASIS NoC}},
Author = {Ryuya Okada},
School = {The University of Aizu},
Year = {2012},
Journal = {Graduation Thesis, The University of Aizu},
Owner = {Khanh},
Timestamp = {2014.11.11}
}
@TechReport{Uesaka2011ONT,
Title = {{OASIS NoC Topology Optimization with Short-Path Link}},
Author = {T. Uesaka},
Institution = {Systems Architecture Group},
Year = {2011},
Month = {March},
Owner = {Khanh},
Timestamp = {2014.11.11}
}
