Real-time Scalable Spiking Neuromorphic Architecture/Chip with Efficient On-chip Learning
Research Background†
...TBU
Research Goal†
The goal of this Doctoral thesis is to research and implement a Deep Spiking Neural Network Architecture with on-chip learning scheme and based on the previously developed schemes NASH1
The expected outputs from this research are:
- (1) An efficient adaptive configuration method which enables reconfiguration of different SNN parameters (spike weights, routing, hidden layers, topology, etc.)
- (2) An Efficient Multicast Fault-tolerant Routing Algorithm for the neurochip
- (3) Efficient on-chip learning Algorithm
- (4) To demonstrate the performance of the algorithms and the system, an FPGA implementation shall be developed and evalauted with several biological SNNs. In addition, a VLSI implementation shall be also developed.
Research schedule†
Step 1: (April 25, 2019, 17:00)†
- Reading 1: Analytic Performance Assessment and High-throughput Low-latency Spike Routing Algorithm and Architecture for Spiking Neural Network Systems, By Vu, March 2019.
- Summarize the paper and make a presentation
Step 2: (TBD)†
Step 3: (TBD)†
Achievement†
On-going Conference and Jnl papers†
Conferences†
Journals†
Survey reports†
Doctoral Dissertation†
Update History†
- April 17, 2019: Page created, Updated by B.
![[PukiWiki]](image/pukiwiki.png "[PukiWiki]")
