Akram Ben Ahmed
Journal papers†
Let us sort them by year.
2013†
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2012†
- 2. A.-M Rahmani, K.R. Vaddina1, K. Latif1, P. Liljeberg, J. Plosila, H. Tenhunen Design and management of high-performance, reliable and thermal-aware 3D networks-on-chip, IET Computers & Digital Techniques, Vol. 6, Issue 5, pp. 308-321, September 2012.
- 4.A.; Fick, D.; Bertacco, V.; Sylvester, D; Blaauw, D; Jin Hu; Chen, G., "A Reliable Routing Architecture and Algorithm for NoCs" Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on , vol.31, no.5, pp.726,739, May 2012
2011†
2008†
Loi, S. Mitra, T. Lee, S. Fujita, and L. Benini, A low-overhead fault tolerance scheme for TSV-based 3D network on chip links, in IEEE/ACM International Conference on Computer-Aided Design, p. 598-602, Nov. 2008
Conference papers†
- 2. Ch. Feng, M. Zhang, J. Li, J. Jiang, Z. Lu, A. Jantsch, A Low-overhead Fault-aware Deflection Routing Algorithm for 3D Network-on-Chip, IEEE Computer Society Annual Symposium on VLSI, pp. 19-24, Chennai-India, July 2011.
3D Topologies and TSVs†
Tools†
Some of the simulators and NoC evaluation platforms built by the NoC research community to study various NoC designs are discussed. Some of the significant features of each of the implementations are also highlighted [referece2012].
- Orion
- A power and area model of on-chip interconnection networks that helps in quick explorations of different NoC designs [see bellow ref] . The motivation behind building such a framework is to estimate the power and area of the interconnect early in the design phase, as they are crucial for an optimized design. As a feature, this framework automatically updates itself as and when a new technology library becomes available. The simulator models all the router components and also the links that form the interconnection network.
- H. S. Wang, X. Zhu, L. S. Peh, and S. Malik, "Orion: A power-performance simulator for interconnection networks," in Proceedings. 35th Annual IEEE/ACM International Symposium on Microarchitecture, p. 294-305, 2002
- Hotspot
- HotSpot [see ref. bellow] is an accurate and fast thermal model suitable for use in architectural studies. It is based on an equivalent circuit of thermal resistances and capacitances that correspond to micro-architecture blocks and essential aspects of the thermal package. The model has been validated using finite element simulation. HotSpot has a simple set of interfaces and hence can be integrated with most power-performance simulators like Wattch [see ref bellow] . The chief advantage of HotSpot is that it is compatible with the kinds of power/performance models used by the computer-architecture community, requiring no detailed design or synthesis description. HotSpot makes it possible to study thermal evolution over long periods of real, full-length applications.
- K. Skadron, M. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan, "Temperature-aware microarchitecture," in Proceedings. 30th Annual International Sympo- sium on Computer Architecture, p. 2-13, June 2003
- D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A framework for architectural-level power analysis and optimizations," in Proceedings of the 27th annual international symposium on Computer architecture, p. 83-94, 2000.
- HSpice
- HSpice [see ref. bellow] is the industry's standard for accurate and comprehensive circuit simulation and offers foundry-certified MOS device models with state-of-the-art simulation and analysis algorithms.
- DevEdit
- DevEdit, a product of Silvaco, Inc., is a tool that can be used to either create a device from scratch or to edit an existing device. DevEdit creates standard Silvaco structures that are easily integrated into Silvaco 2-D or 3-D simulators and other support tools.
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