3D-ONoC-Verilog の履歴(No.1)

• 履歴一覧
• 差分 を表示
• 現在との差分 を表示
• ソース を表示
• 3D-ONoC-Verilog へ行く。
  • 1 (2014-04-17 (木) 06:13:35)
  • 2 (2014-04-17 (木) 07:18:56)
  • 3 (2014-05-20 (火) 08:25:09)
  • 4 (2014-05-29 (木) 08:51:46)

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Hiroki Tanaka

3D-OASIS-Network-on-Chip Verilog Source†

2x2x2 3D-OASIS-NoC full project zip

TOP_test.v Random Number Generator Test bench

defines.v define file for parameters initialization

network.v Top-module: 2x2x2 mesh topology

• router.v Router module

• input_port.v Input port module

• fifo.v FIFO input buffer module

• route.v LA-XYZ routing module

• sw_alloc.v ''Switch allocator module
  • stop_go.v Stop-Go flow control module
  • matrix_arb_formultistage.v Matrix arbiter module

• crossbar.v Crossbar module
  • mux_out.v Crossbar module

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CNI Verilog Code†

2D-OASIS-NoC Verilog source†

QueueCore Verilog source†

SEA Verilog source†

QSoC Verilog source†

QSoC Verilog source code†

FaRM Verilog source code†

QASM C source code†

Qsim C source code†

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