Ben Abdallah Abderazek [ベンアブダラ アブデラゼク]

Last updated on 06/11/2018

Books (専門書)


Refereed Journal Paper (査読付き学術雑誌論文)

  • Khanh N. Dang, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan-Tu Tran,”2D Parity Product Code for TSV online fault correction and detection”, Submitted, IEEE Transactions on Emerging Topics in Computing, May 7, 2018.
  • Khanh N. Dang,  Akram Ben Ahmed, Yuichi Okuyama, Abderazek Ben Abdallah, ”Scalable Design Methodology and Online Algorithm for TSV-cluster Defects Recovery in Highly Reliable 3D-NoC Systems”, IEEE Transactions on Emerging Topics in Computing, 2017 (in press). DOI: 10.1109/TETC.2017.2762407
  • Khanh N. Dang, Akram Ben Ahmed, Xuan-Tu Tran, Yuichi Okuyama, Abderazek Ben Abdallah, ”A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 25, Issue: 11, pp. 3099 – 3112, vol. 2017.  DOI: 10.1109/TVLSI.2017.2736004
  • Achraf  Ben Ahmed, Tsutomu Yoshinaga, Abderazek Ben Abdallah, “Scalable Photonic Networks-on-Chip Architecture Based on a Novel Wavelength-Shifting Mechanism”, IEEE Transactions on Emerging Topics in Computing, 2017. DOI: 10.1109/TETC.2017.2737016
  • Khanh N. Dang, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”A Low-overhead Soft-Hard Fault Tolerant Architecture, Design and Management Scheme for Reliable High-performance Many-core 3D-NoC Systems”, Journal of Supercomputing (2017) 73:2705–2729
  • Achraf Ben Ahmed, A. Ben Abdallah, Architecture and Design of Real-Time Systems for Elderly Health Monitoring, J. of Embedded Systems, 2017, Vol.9, No.5, pp.484 – 494,  DOI: 10.1504/IJES.2017.10007717
  • Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”Microring Fault-resilient Photonic Network-on-Chip for Reliable High-performance Many-core Systems”, Journal of Supercomputing, 2016, doi: 10.1007/s11227-016-1846-0
  • Akram Ben Ahmed, Abderazek Ben Abdallah, ”Adaptive Fault-Tolerant Architecture and Routing Algorithm for Reliable Many-Core 3D-NoC Systems”, Journal of Parallel and Distributed Computing, Volumes 93–94, July 2016, Pages 30-43, ISSN 0743-7315, doi:10.1016/j.jpdc.2016.03.014
  • Achraf Ben Ahmed, Abderazek Ben Abdallah, “Hybrid Silicon-Photonic Network-on-Chip for Future Generations of High-performance Many-core Systems,” Journal of Supercomputing, Dec. 2015, Vol. 71, Issue 12, pp 4446-4475. DOI: 10.1007/s11227-015-1539-0
  • Akram Ben Ahmed, A. Ben Abdallah,”Graceful Deadlock-Free Fault-Tolerant Routing Algorithm for 3D Network-on-Chip Architectures”, Journal of Parallel and Distributed Computing, 74/4 (2014), pp. 2229-2240.
  • Akram Ben Ahmed, A. Ben Abdallah, ”Architecture and Design of High-throughput, Low-latency and Fault-Tolerant Routing Algorithm for 3D-Network-on-Chip”, Journal  of Supercomputing, December 2013, Volume 66, Issue 3, pp 1507-1532
  • Abderazek Ben Abdallah, M. Masuda, A. Canedo, K. Kuroda, “Natural Instruction Level Parallelism-aware Compiler for High-Performance QueueCore Processor Architecture,” Journal of Supercomputing, Volume 57, Number 3, pp. 314-338, Sept. 2011.Canedo,
  • Arquimedes Canedo, Abderazek Ben Abdallah, Masahiro Sowa, “Compiling for Reduced Bit-Width Queue Processors”, Journal of Signal Processing Systems, Volume 59, Number 1, 45-55, 2010.
  • Arquimedes Canedo, Abderazek Ben Abdallah,  Masahiro Sowa, “Efficient Compilation for Queue Size-Constrained Queue Processors”, Journal of Parallel Computing, Vol.35, pp. 213-225, 2009.
  • Arquimedes Canedo, Abderazek Ben Abdallah, Masahiro Sowa, “Design and Implementation of a Queue Compiler”, Journal of Microprocessors and Microsystems, Vol. 33, Issue 2, pp. pp. 29-138, 2009.
  • Arquimedes Canedo, Abderazek Ben Abdallah, Masahiro Sowa, “Compiler Support for Code Size Reduction using a Queue-based Processor”, Transactions on High-Performance Embedded Architectures and Compilers, Vol. 2, Issue 4, pp. 269-285, 2009.
  • Abderazek Ben Abdallah, A. Canedo, T. Yoshinaga, M. Sowa, “The QC-2 Parallel Queue Processor Architecture”,  Jnl. of Parallel and Distributed Computing, Vol. 68, No. 2, pp. 235-245, 2008.
  • Md. Musfiquzzaman Akanda, Abderazek Ben Abdallah, and Masahiro Sowa, “Dual-Execution Mode Processor Architecture,”Journal of Supercomputing, Vol. 44, No. 2, pp. 103-125, 2008.
  • Ben Abdallah, and M. Sowa, “A New Code Generation Algorithm for 2-offset Producer Order Queue Computation Model”, A. Canedo,  Journal of Computer Languages, Systems & Structures, Vol. 34, Issue 4, pp. 184-194, 2007
  • Ben Abdallah, and M. Sowa, “Advanced Power Management Techniques for Mobile Communication Systems”, Journal of Computer Research, Vol. 14, No.2, pp. 109-128, 2007
  • Md. Musfiquzzaman Akanda, A. Ben Abdallah, and M. Sowa, “Dual-Execution Mode Processor Architecture For Embedded Applications”, Journal of Mobile Multimedia, Vol. 3, No.4, Dec. 2007, pp. 347-370.
  • Abderazek Ben Abdallah, T. Yoshinaga, M. Sowa, “High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core”, Journal of Supercomputing, Vol. 38, Number 1, pp. 3-15, 2006.
  • Abderazek Ben Abdallah, Sotaro Kawata, M. Sowa, “Design and Architecture for an Embedded 32-bit Queue Core”, Journal of Embedded Computing, Special Issue in embedded single-chip multicore architectures, Vol. 2, No. 2, pp. 191-205, 2006.
  • Viet, T. Yoshinaga, A. Ben Abdallah, and M. Sowa, “Construction of Hybrid MPI-OpenMP Solutions for SMP Clusters”, IPSJ Transactions on Advanced Computing Systems, Vol.46, pp.25-37, Jan. 2005.
  • Sowa, A. Ben Abdallah, and T. Yoshinaga, “Processor Architecture Based on Produced Order Computation Model”, Journal of Supercomputing, Vol. 32, No. 3, pp. 217-229, June 2005.
  • Abderazek Ben Abdallah, Mudar Sarem, Masahiro. Sowa, “Dynamic Fast Issue Mechanism (DFI) for Dynamic Scheduled Processors”, IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Science, Vol. E83-A No.12 pp.2417-2425, Dec. 2000.

Other Publications (その他の著作)

  • Abderazek Ben Abdallah, “Efficient Parallel ECG Processing Algorithm and Design of Flexible Health Monitoring System for Elderly People”, Innovation Research Journal, March    2010, pp. 24-27.
  • Nakanishi, A. Canedo, A. Ben Abdallah, and M. Sowa, “Optimizing Reaching Definitions Overhead in Queue Processors”, Journal of Convergence Information                    technology, 2007, Vol. 2, No. 4, pp. 36-40, 2007
  • Abderazek Ben Abdallah, “Local Industries, Government Organizations and Educational Institutions Interaction – Part I: Universities-Industry Cooperation The Japanese Case”, ARISE, Vol. 1 No. 2 (2005) 43-44, 2005.

Refereed International Conference Papers (査読付き国際会議論文)

  • The H. Vu, Ryunosuke Murakami, Yuichi Okuyama, Abderazek Ben Abdallah, ”Efficient Optimization and Hardware Acceleration of CNNs towards the Design of a Scalable Neuro-inspired Architecture in Hardware”, IEEE International Conference on Big Data and Smart Computing (BigComp), Shanghai, China, January 15-18, 2018.
  • Khanh N. Dang, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”Reliability Assessment and Quantitative Evaluation of Soft-Error Resilient 3D NoC System”, 25th IEEE Asian Test Symposium (ATS’16), November 21-24, 2016
  • Khanh N. Dang, Yuichi Okuyama, Abderazek Ben Abdallah, ”Soft-Error Resilient Network-on-Chip for Safety-Critical Applications”, 2016 IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), June 27 – 29, 2016
  • Khanh N. Dang, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, “A Soft-Error Resilient 3D Network-on-Chip Router for Highly-reliable Multi-core Systems”, IEEE 7th International Conference on Awareness Science and Technology (iCAST 2015), Sep. 22-24, 2015.
  • Achraf Ben Ahmed, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”Hybrid Photonic NoC based on Non-blocking Photonic Switch and Light-weight Electronic Router”, of the IEEE International Conference on Systems, Man, and Cybernetics (SMC2015), Oct. 9-12, 2015.
  • Michael Meyer, Akram Ben Ahmed, Yuichi Okuyama, Abderazek Ben Abdallah, ”Microring Fault-resilient Optical Router for Reliable Network-on-Chip Systems”, of 9th IEEE International Symposium on Embedded Multicore/Manycore SoCs (MCSoC-15), Sept. 2015.
  • Michael Meyer, Akram Ben Ahmed, Yuki Tanaka, Abderazek Ben Abdallah, “On the Design of a Fault-tolerant Photonic Network-on-Chip,” of the IEEE International Conference on Systems, Man, and Cybernetics (SMC2015), Oct. 9-12, 2015.
  • Achraf Ben Ahmed, Yuichi Okuyama, Abderazek Ben Abdallah,”Non-blocking Electro-optic Network-on-Chip Router for High-throughput and Low-power Many-core Systems”,  of the World Congress on Information Technology and Computer Applications 2015, June 11-13, 2015
  • Achraf Ben Ahmed, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah,”Efficient Router Architecture, Design and Performance Exploration for Many-core Hybrid Photonic Network-on-Chip (2D-PHENIC)”, Proc. Of the International Conference on Information Science and Control Engineering, 04/2015.
  • Ben Ahmed, M. Meyer, Y. Okuyama, and A. Ben Abdallah, ”Adaptive Error- and Traffic Aware Router Architecture for 3D Network-on-Chip Systems”, IEEE Proceedings of the 8th International Symposium on Embedded Multicore/Manycore SoCs (MCSoC-14), pp. 197-2014, Sept. 2014.
  • Achraf Ben Ahmed, A. Ben Abdallah, ”PHENIC: Towards Photonic 3D-Network-on-Chip Architecture for High-throughput Many-core Systems-on-Chip”, IEEE Proceedings of the 14th International Conference on Sciences and Techniques of Automatic control and computer engineering, 2013
  • Akram Ben Ahmed, A. Ben Abdallah, ”Fault-tolerant Routing Algorithm with Deadlock Recovery Support for 3D-NoC Architectures”, IEEE Proceedings of the 7th International Symposium on Embedded Multicore SoCs, Sept. 2013
  • Achraf Ben Ahmed, A. Ben Abdallah, ”Hardware/Software Prototyping of Dependable Real-Time System for Elderly Health Monitoring”, IEEE Proc. of the World Congress on Computer and IT, ICMAES, June 2013. 
  • Akram Ben Ahmed, T. Ouchi, S. Miura, A. Ben Abdallah, ”Run-Time Monitoring Mechanism for Efficient Design of Application-specific NoC Architectures in Multi/Manycore Era”, Proc. IEEE 6th International Workshop on Engineering Parallel and Multicore Systems (ePaMuS2013′), July 2013.
  • Akram Ben Ahmed, A. Ben Abdallah, ”Low-overhead Routing Algorithm for 3D Network-on-Chip”, IEEE Proc. of The Third International Conference on Networking and Computing (ICNC’12), pp. 23-32, 2012.
  • Akram Ben Ahmed, A. Ben Abdallah, ”LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture”, IEEE Proceedings of the 6th International Symposium on Embedded Multicore SoCs (MCSoC-12), pp. 167-174, 2012.
  • Achraf Ben Ahmed, Yumiko Kimezawa, A. Ben Abdallah, ”Towards Smart Health Monitoring System for Elderly People”, IEEE Proceedings of The 4th International Conference on Awareness Science and Technology, pp. 248-253, 2012.
  • Akram Ben Ahmed, A. Ben Abdallah, ”ONoC-SPL Customized Network-on-Chip (NoC) Architecture and Prototyping for Data-intensive Computation Applications”, IEEE Proceedings of The 4th International Conference on Awareness Science and Technology, pp. 257-262, 2012.
  • A. Ben Abdallah, M. Masuda, A. Canedo, K. Kuroda, ”Natural Instruction Level Parallelism-aware Compiler for High-Performance Processor Architecture”, The Journal of Supercomputing, Volume 57, Number 3, pp. 314-338, Sept. 2011.
  • A. Ben Ahmed, A. Ben Abdallah, K. Kuroda, ”Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoCs”, IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), Nov. 2010. (Best Paper Award)
  • K. Mori, A. Esch, A. Ben Abdallah, K. Kuroda, ”Advanced Design Issues for OASIS Network-on-Chip Architecture”, IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), Nov. 2010, pp. 74-79.
  • A. Ben Abdallah, Y. Haga, K. Kuroda, ”An Efficient Algorithm and Embedded Multicore Implementation for ECG Analysis in Multi-lead Electrocardiogram Records”, IEEE Proc. of the 39th the International Conference on Parallel Processing Workshop, San Diego, pp.99-103, Sept. 13-16, 2010.
  • M. Masuda, A. Ben Abdallah, A. Canedo, ”Software and Hardware Design Issues for Low-Complexity High-Performance Processor Architecture”, IEEE ICPPW’09 Proc. of the 2009 International Conference on Parallel Processing Workshops, pp. 558-565, 2009.
  • Y. Haga, A. Ben Abdallah, and K. Kuroda, ”Embedded MCSoC Architecture and Period-Peak Detection (PPD) Algorithm for ECG/EKG Processing”, The 19th Intelligent System Symposium (FAN 2009), pp.298-303, Sep. 2009.
  • S. Miura, A. Ben Abdallah, and K. Kuroda, ”PNoC – Design and Preliminary Evaluation of a Parameterizable NoC for MCSoC Generation and Design Space Exploration”, The 19th Intelligent System Symposium (FAN 2009), pp.314-317, Sep. 2009.
  • K. Mori, A. Ben Abdallah, and K. Kuroda, ”Design and Evaluation of a Complexity-Effective Network-on-Chip Architecture on FPGA”, The 19th Intelligent System Symposium (FAN 2009), pp.318-321, Sep. 2009.
  • M. Masuda, A. Canedo, A. Ben Abdallah, ”Efficient Code Generation Algorithm for Natural Instruction Level Parallelism-aware Queue Architecture”, The 19th Intelligent System Symposium (FAN 2009), pp.308-313, Sep. 2009.(Best Presentation Award).
  • T. Maekawa, A. Ben Abdallah, and K. Kuroda, ”Single Instruction Dual-Execution Model Processor Architecture”, Proc. IEEE/IFIP Int’l Conf. on Embedded and Ubiquitous Computing (EUC2008), pp.30-36, Dec. 2008.
  • H. Hoshino, A. Ben Abdallah, and K. Kuroda, ”Advanced Optimization and Design Issues of a 32-bit Embedded Processor Based on Produced Order Queue Computation Model”, IEEE/IFIP Int’l Conf. on Embedded and Ubiquitous Computing (EUC2008),pp.16-22, Dec.2008.
  • A. Canedo, A. Ben Abdallah, and M. Sowa, ”Quantitative Evaluation of Common Sub-expression Elimination on Queue Machines”, Proc. IEEE Int’l Sym. on Parallel Architectures, Algorithms, and Networks (I-SPAN 2008), pp.25-30. 2008.
  • A. Ben Abdallah, T Yoshinaga, and M. Sowa, ”Mathematical Model for Multiobjective Synthesis of NoC Architectures”, IEEE Proc. of the 36th International Conference on Parallel Processing, Sept. 2007.
  • A. Canedo, A. Ben Abdallah, and M. Sowa, ”Queue Register File Optimization Algorithm for QueueCore Processor”, Proc. IEEE 19th International Symposium on Computer Architecture and High-Performance Computing (SBAC-PAD 2007), pp. 169-176, 2007.
  • A. Canedo, A. Ben Abdallah, and M. Sowa, ”An Efficient Code Generation Algorithm for Code Size Reduction using 1-offset P-Code Queue Computation Model”, Proc. IFIP International Conference on Embedded and Ubiquitous Computing (EUC07), pp. 196-208, 2007
  • A. Canedo, A. Ben Abdallah, and M. Sowa, ”Compiler Framework for an Embedded 32-bit Queue Processor”, Proc. of the International Conference on Convergence Information Technology (ICCIT07), Gyeongju, South Korea, pp. 877-884, 2007.
  • A. Ben Abdallah, T. Yoshinaga, and M. Sowa, ”Scalable Core-Based Methodology and Synthesizable Core for Systematic Design Environment in Multicore SoC (MCSoC)”, Proc. IEEE 35th International Conference on Parallel Processing Workshops, Aug. 14-18th, pp. 345-352, 2006.
  • A. Ben Abdallah, Masahiro Sowa, ”Basic Network-on-Chip Interconnection for Future Gigascale MCSoCs Applications: Communication and Computation Orthogonalization”, Proc. of the Joint Symposium on Science, Society and Technology (JASSST2006), pp. 1-7, Dec. 4-9th, 2006.
  • A. Ben Abdallah, M. Arsenji, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core”, Proc. of International Conference on Embedded and Ubiquitous Computing (EUC2005), LNCS Vol.3824, pp. 340-349, 2005.
  • M. Akanda, A. Ben Abdallah, S. Kawata, and M. Sowa, ”An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture”, Proc. of International Conference on Embedded and Ubiquitous Computing (EUC2005), LNCS Vol.3824, pp. 77-86, Dec. 2005.
  • A. Markovskij, A. Ben Abdallah, S. Kawata, and M. Sowa, ”Architecture of Produced-order Parallel Queue Processor: Preliminary Evaluation”, Proc. of the 38th International Symposium on Microarchitecture (MICRO-38), Nov. 2005.
  • Ta Quo Viet, T. Yoshinaga, and A Ben Abdallah, ”Performance Enhancement for Matrix Multiplication on an SMP PC Cluster”, Summer United Workshops on Parallel, Distributed and Cooperative Processing, August 2005.
  • A. Ben Abdallah, Markov Arsenji, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Queue Processor for Novel Queue Computing Paradigm Based on Produced Order Scheme”, Proc. IEEE of the 7th High-Performance Computing and Grid in Asia Pacific Region (HPCAsia2004), pp. 169-177, July 2004.
  • Shigeta, L.-Q. Wang, N. Yagishita, A. Ben Abdallah, T. Yoshinaga, and M. Sowa, ”QJava: Integrate Queue Computational Model into Java”, Proc. of the Joint Japan-Tunisia Workshop on Computer Systems and Information Technology (JT-CSIT’04), July 2004.
  • A. Markovskij, M. Sowa, A. Ben Abdallah, S. Shigeta, and T. Yoshinaga, ”Design of Producer-Order Parallel Queue Processor Architecture”, Proc. of International Workshop on Modern Science and Technology (IWMST 2004), September 2-3, 2004.
  • M. Akanda, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”High-performance Hybrid Processor Architecture with Efficient Hardware Usability”, Proc. of International Workshop on Modern Science and Technology (IWMST 2004), September 2-3, 2004.
  • H. Sasaki, Y. Okumura, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Theoretical Evaluation of Simultaneous Multi-threading Parallel Queue Processor Architecture”, Proc. International Conference on Circuits/Systems, Computers and Communications, July 2004.
  • A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”On the Design of a Register Queue Based Processor Architecture (FaRM-rq)”, Proc. of the International Symposium of Parallel and Distributed Processing and Applications (ISPA 2003), pp.248-262, July 2003.
  • L. Q. Wang, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”QJAVAC: Queue-Java Compiler Design for High Parallelism Queue Java Bytecode”, Proc. of International Technical Conference in Circuits/Systems, Computers and Communications (ITC-CSCC2003), pp. 900-903, July 2003.
  • Tao. Q. Viet, T. Yoshinaga, A. Ben Abdallah, and M. Sowa, ”A Hybrid MPI-OpenMP Solution for a Linear System on a Cluster of SMPP”, SACSIS03, pp.299-306, 2003.
  • T. Q. Viet, T. Yoshinaga, A. Ben Abdallah, and M. Sowa, ”A Hybrid MPI-OpenMP Solution for a Linear System on a Cluster of SMPs”, Proc. of Symposium on Advanced Computing Systems and Infrastructures, pp.299-306, 2003.
  • A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Complexity Analysis of a Functional Assignment Register Microprocessor”, Proc. of the Int. Workshop on Modern Science and Technology (IWMST02), pp.116-123, Sep. 2002.
  • A. Ben Abdallah, Mudar Sarem, and M. Sowa, ”Dynamic Fast Issue Mechanism (DFI) for Dynamic Scheduled Processors”, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Science, Vol. E83-A No.12 pp.2417-2425, Dec. 2000.
  • A. Ben Abdallah, K. Nikolova, and M. Sowa, ”FARM-Queue Mode: On a Practical Queue Execution Model”, Proc. of the Int. Conf. on Circuits and Systems, Computers and Communications, pp.939-944, July 2001.
  • Kiriuka Nikolova, A. Ben Abdallah, and M. Sowa, ”Dynamical Critical Path Parallelism-Independent Scheduling Algorithm for Distributed Computing Systems”, Proc. of the International Technical Conference on Circuits and Systems, Computers and Communications, pp. 929-934, July 2001.
  • A. Ben Abdallah, and M. Sowa, ”DRA: Dynamic Register Allocator Mechanism for FaRM Microprocessor”, Proc. of the 3rd International Workshop on Advanced Parallel Processing Technologies (APPT’99), pp.131-136, October 1999.
  • A. Ben Abdallah, M. Sarem, and M. Sowa, ”A Survey on the advances of Disc I/O performance metrics”, Proc. of International Conference on Robotics, Vision and Parallel Processing, pp. 522-527, July 1999.
  • A. Ben Abdallah, A. Kazi, and L. L. Shan, ”Multi-Function Interface Board for Teaching Topics and Development System”, APST97, Yata, PRC. Pp.134-139, Sep. 1997
  • L. L. Shan, L. Liu, and A. Ben Abdallah, ”The Master-Slave Two Level Distributed Microcomputer Measuring and Monitoring System”, ISMTIT, Japan, pp. 161-164, 1996

Domestic Conference Papers (国内研究会)

  • Ryunosuke Murakami, Yuichi Okuyama, Abderazek Ben Abdallah, ”Animal Recognition and Identification with Deep Convolutional Neural Networks for Farm Monitoring”, Information Processing Society Tohoku Branch Conference, Koriyama, Japan, Feb. 10, 2018
  • Yuji Murakami, Yuichi Okuyama, Abderazek Ben Abdallah, ”SRAM Based Neural Network System for Traffic-Light Recognition in Autonomous Vehicles”, Information Processing Society Tohoku Branch Conference, Koriyama, Japan, Feb. 10, 2018
  • Kanta Suzuki, Yuichi Okuyama, Abderazek Ben Abdallah, ”Hardware Design of a Leaky Integrate and Fire Neuron Core Towards the Design of a Low-power Neuro-inspired Spike-based Multicore SoC”, Information Processing Society Tohoku Branch Conference, Koriyama, Japan, Feb. 10, 2018
  • A. Ben Abdallah, T. Yoshinaga, and M. Sowa, ”Rapid FPGA Prototyping of a Queue Processor Core for Embedded Computing”, Proc. of 67th Conf. of Information Processing Society of Japan, March 2~4, 2005.
  • A. Ben Abdallah, M. Arsenji, K. Kiuchi, M. Akanda, S. Shigeta, T. Yoshinaga, and M. Sowa, ”PQPpfB: Parallel Queue Processor Architecture in Verilog-HDL”, Proc. of 66th Information Processing Society of Japan, pp. 3F-4, March 2004.
  • T. Viet, T. Toshinga, A. Ben Abdallah, and M. Sowa, ”Optimization for Hybrid MPI-OpenMP Programs on a Cluster of SMPs”, SACSIS 2004.
  • A. Musfiquzzaman, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Queue Computation Mechanism For Parallel Execution in Parallel Queue Processor”, Proc. of Information Processing Society of Japan, Vol. 60, pp. 3F-4, 2004.
  • A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Architectural Issues in the Design of a High-Performance Parallel Queue Processor”, Proc. of 4th Tunisia-Japan Symposium on Science and Technology (TJASSST2003), April 2003.
  • A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Reduced Bit-Width Instruction Set Architecture for Q-mode Execution in Hybrid Processor Architecture (FaRM-rq)”, Proc. of Information Processing Society of Japan, pp. 19-23, June 2003.
  • L. Wang, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Fast, Effective Instruction Generation Algorithm For Queue-Java Compiler (QJAVAC)”, Proc. of Information Processing Society of Japan, Vol.2003, No.40, pp.55-60, 2003.
  • L. Wang, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”An Ambiguous Context-Free Grammar for Deterministic Parsing In Queue-Java Compiler”, Proc. of Information Processing Society of Japan, Vol.2003, No.62, pp.7-12, 2003.
  • L. Wang, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”QJAVAC: Queue-Java Compiler Design for High Parallelism Queue Java”, Proc. of IIEICE Technical Conference, 2003.
  • A. Ben Abdallah, K. Nikolova T. Yoshinaga, and M. Sowa, ”FARM QUEUE MODE: On a Practical Queue Execution Model (QEM)”, TIWSS’01, October 2001.”’
  • A. Ben Abdallah, K. Nikolova, and M. Sowa, ”FARM-Queue Execution Model: Towards an Alternative Computing Paradigm”, Proc. of IPSJ Symposium, Yokohama pp.99-100, March 2000.
  • A. Ben Abdallah, M. Sarem., and M. Sowa, ”Acyclic DFG on a Queue Machine”, Proc. of JSPP, Tokyo, pp.119-120, 2000.
  • A. Ben Abdallah, and M. Sarem, ”Instruction Scheduling System for Superscalar Processor”, JSPP, Tokyo, pp.161, Apr. 2000.

Invited Talks & Lectures (招待講演)

  • Abderazek Ben Abdallah, ”Neuro-inspired Computing Systems & Applications”, Keynote Speech, 2018 International Conference on Intelligent Autonomous Systems (ICoIAS’2018), Singapore, March 1-3, 2018
  • Abderazek Ben Abdallah, ”Neuro-Inspired Adaptive Manycore SoCs and Applications”, Keynote Speech, International Conference on Control, Automation and Robotics, Nagoya, April 22-24, 2017.
  • Abderazek Ben Abdallah, ”Developing a Mindset for Innovation & Entrepreneurship”, 1st ACM Chapter Networking Seminar on Globalization & Innovative Thinking, 2017/11/26, University of Aizu
  • Abderazek Ben Abdallah, ‘Adaptive SoCs for Smart Autonomous Systems”, Keynote Speech, 17th International Conference on Sciences and Techniques of Automatic control & Computer Engineering (STA2016), Sousse, December 19-21, 2016.
  • Invited course on Distributed Computing, Huazhong University of Science and Technology (HUST), China, 2016
  • Keynote Speech, AUST International Conference of Technology, Oct. 12-13, 2015. Title: Heterogeneous Systems for Future Computing
  • Invited course on Distributed Computing, Huazhong University of Science and Technology (HUST), Wuhan, China, 2015
  • Abderazek Ben Abdallah, ‘Adaptive SoCs for Smart Autonomous Systems”, Keynote Speech, 17th International Conference on Sciences and Techniques of Automatic control & Computer Engineering (STA2016), Sousse, December 19-21, 2016.
  • Abderazek Ben Abdallah, ”On-Chip Optical Interconnects: Prospects and Challenges.” 6th International Conference on Soft Computing and Pattern Recognition (SoCPAR2014), August 11-14, 2014. 
  • Invited course on Distributed Computing, Huazhong University of Science and Technology (HUST), China, 2014
  • Keynote Speech, IEEE PCSJ 2nd Technical Meeting, Nov. 2, 2013. Title: Towards the Development of a Smart System for Wireless Body Area Networks”.
  • Invited lectures on Network-on-Chip, Hong Kong University of Science and Technology (KUST), China, Hong Kong Special Administrative Region, 2013
  • Invited course on Distributed Computing, Huazhong University of Science and Technology (HUST), China, 2013
  • Invited course on Distributed Computing, Huazhong University of Science and Technology (HUST), China, 2012
  • Invited lectures on Network-on-Chip, Hong Kong University of Science and Technology (KUST), China, Hong Kong Special Administrative Region, 2012
  • Invited course on Parallel/Distributed System, Huazhong University of Science and Technology (HUST), China, 2011
  • Invited lectures on Network-on-Chip, Hong Kong University of Science and Technology (KUST), China, Hong Kong Special Administrative Region,2011
  • Invited lectures on Network-on-Chip, Hong Kong University of Science and Technology (KUST), China, Hong Kong Special Administrative Region, 2010
  • Invited lectures, African University of Science and Technology, Abuja, Nigeria, 2009-

Teaching (教育・講師歴)

Current Courses

  • Introduction to Computer Systems, Undergraduate level, UoA, 2018 – present
  • Computer Architecture, Undergraduate level, UoA, 2018 – present
  • Advanced Computer Organization, Graduate level, UoA, 2018 – present
  • Embedded Real-Time Systems, Graduate level, UoA, 2018 – present
  • Parallel Computer Systems, Undergraduate level, UoA, 2018 – present

Previous Courses

  • SCCP-001 – Student Cooperative Class Project (System-on-Chip Design), 2009-2010, UoA
  • Computer System Engineering, Undergraduate level (2008-2018), UoA
  • Embedded Systems, Undergraduate level (2008-2016), UoA
  • Logic Circuit Design Exercises, Undergraduate level (2008-2018), UoA
  • Computer Architecture Exercises, Undergraduate level (2008-2018), UoA
  • Multicore Computing, Graduate level (2010-2015), UoA

Academic Activities (学会活動等)

Educational, Research, and Review Support at other Institutions (他大学等教育支援)

  • External reviewer for The Austrian Science Fund (FWF), Austria, 4/2018
  • External Ph.D. examiner, University of Otago, New Zealand, 2017 
  • External Ph.D. examiner, Murdoch University, Australia, 2014.  
  • External reviewer for Research Grants Council (RGC) of the local Government of Hong Kong, Hong Kong, PRC, 2012.  
  • Invited intensive lectures, Hong Kong University of Science and Technology (香港科技大学), China, Hong Kong Special Administrative Region, 2010-2013  
  • Invited intensive course, Huazhong University of Science and Technology (华中科技大学), Wuhan, China, 2010-2016  
  • Invited intensive course, African University of Science and Technology (AUST), Abuja, Nigeria,  2008-2016

Memberships of Academic Societies (所属学協会)

  • Senior Member of IEEE (Institute of Electrical and Electronics Engineers)
  • Senior Member of ACM (Association for Computing Machinery)
  • Member of  IEICE (The Institute of Electronics, Information, and Communication Engineers)

Committees and Councils Involvement (委員会・審議会等)

  • Served on many University’s Committees and Councils at The University of Aizu (UoA), Aizu-Wakamatsu, Japan, 2007-present
  • Served on many University’s Committees at The University of Electro-Communications at Tokyo (UEC), Tokyo, Japan, 2002-2007
  • Member of the Governmental High-Level Committee for Science and Technology, Tunisia (Nominated  by the President of the country), 2009-2011
  • Director, the Support Association for International Students of the University of Aizu (SAISUA), Aizu-Wakamatsu, Japan, 2008-2011
  • Guest Editor, IEEE Transactions on Emerging Topics in Computing, Special Issue on Parallel Programming and Architecture Support for Many-core Embedded Systems, 2014.
  • Associate Editor, Journal of Embedded Systems, Inner Science, 2015 – present
  • Editor, Journal of Embedded Systems, Inner Science, 2013-2015
  • Guest Editor, Special Issue on Embedded Multicore and Many-core Architectures, Journal of Embedded Systems (IJES), InderScience, 2013.
  • Editor, Journal of Adaptive and Innovative Systems, InderScience, 2013-present.
  • Editor, Advances in Next Generation Mobile Multimedia, Book Series, 2007-2009
  • Editor, Journal of Mobile Computing and Multimedia Communications (IJMCMC), 2007
  • Editor, Journal of Convergence Information Technology, 2008-2010.
  • Reviewer (past & present): Journal of Parallel and Distributed Computing; IEEE Computer; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems; IEEE Micro; IEEE Network Magazine; IET Journal of Circuits, Devices & Systems;  Journal of Parallel Computing; Journal of Supercomputing; IEICE Transactions; Integration: The VLSI Journal; ACM Journal on Emerging Technologies in Computing Systems.

Involvement in Conference and Research Meetings (会議・研究会等)

  • Founder and Steering Chair of the IEEE Symposium on Embedded Multicore/Manycore Systems-on-chip (MCSoC) Series, 2004 – present
  • Program member of the IEEE Symposium on Low-Power and High-Speed Chips (COOLChips), Yokohama, 2010 – present 
  • Program Co-chair, 5th International Workshop of Engineering Parallel and Multicore Systems, July 4-6, 2012, Palermo, Italy.
  • Publication Chair, 4th International Conference on Frontier of Computer Science and Technology (FCST2009), Shanghai, 2009.
  • Program Chair, IEEE International Conference on Embedded Software and Systems, Hangzhou, Zhejiang, China, 2009.
  • General Chair, 3rd International Workshop on Embedded Single and Multicore Systems on Chips, In conjunction with 36th ICPP-2007, China, 2007
  • Steering Chair, 2nd International Workshop on SoC and MCSoC Design with MoMM 2006, Yogyakarta, Indonesia, 2006.
  • General Co-chair, 8th International Workshop on High-Performance Scientific and Engineering Computing, Columbus, Ohio, USA, August 18, 2006
  • Program Co-chair, International Conference on Computer design, CDES-05, Las Vegas, 2005.
  • Program Chair, Joint Japan-Tunisia Workshop on Computer Systems and Information Technology (JT-CSIT2004), The University of Electro-Communications, Tokyo, Japan, 2004.
  • TPC member for +30 International conferences and workshops

Patents (特許)

  • 特許第6284177号(登録日2018.2.9) ベンアブダラ アブデラゼク,「誤り耐性ルータ、これを使用するIC、及び誤り耐性ルータの制御方法」[A fault-tolerant router, an IC having the same, and a method for controlling the fault tolerant router,”], 特願2013-262523, Japan.
  • Abderazek Ben Abdallah, Khanh N. Dang, Masayuki Hisada, A TSV fault-tolerant router system for 3D-Networks-on-Chip, 特願 2017-218953, Japan.
  • Abderazek Ben Abdallah, Methods, Algorithm, and Robust Fault-tolerant Router for Reliable Networks-on-Chip,特願 2016-100732, Japan
  • Abderazek Ben Abdallah, A Photonic Network-on-Chip System employing non-blocking photonic switches with respective control units, and a method of setting up the Photonic Network-on-Chip, 特願2015-196698, Japan

Awards (受賞歴)

  • Certificate of Appreciation, Huazhong University of Science and Technology, Wuhan, China, 993
  • Certificate of Appreciation, Huazhong University of Science and Technology, Wuhan, China, 1994
  • Best Paper Award at Eighth International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2007), Adelaide, Australia, Dec. 3-6, 2007
  • Best Presentation Award at The 19th Intelligent System Symposium (FAN2009), Aizu-Wakamatsu, Japan (with my student), Sept. 2009
  • Best Paper Award at the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), Fukuoka, Japan, 2010
  • President Prize for Scientific Research and Technology (TKD), Tunis, Tunisia, July 2010

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