How to use High-level synthesis
R. Murakami, How to use High-level synthesis, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, May 13, 2019.
Edge TPU Coral Dev Board Tutorial
Vu The, Edge TPU Coral Dev Board: A tutorial, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, May 13, 2019.
PHENIC: Photonics NoC Design
Achraf Be Ahmed, Photonic NoC Design Tutorial, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, January 18, 2016.
OASIS: On-chip Router Hardware Design
Akram Ben Ahmed, OASIS 3D Fault Tolerant Router Hardware Physical Design with TSV, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, May 28, 2015.
OASIS 3D Fault Tolerant Router Hardware Physical Design with TSV, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, July 8, 2014.
- Tutorial 0: Setting the Network Driver
- Tutorial 1: Designing with Quartus II, SOPC and FPGA
- Tutorial 2: Nios II IDE tutorial
- Tutorial 3: Debugging with Nios II
- Tutorial 4: Nios II processor , Nios II instruction set reference
- Tutorial 5: Running programs on the DE2 FPGA board
- Tutorial 6: Designing with SOPC
- Tutorial 7: TOPPERS RTOS
- VDEC Web Site. Go to this site to get design tools (user name and pass required).
- HSPICE, HSPICE Tutorial
- Unfair OCLs
- Parallel Board , ( site )
- Xilinx 3D IC FPGA
- UAV Laboratory
Going from GDSII to OASIS, Philippe Morey Chaisemartin Xyalis
BookSim is a cycle-accurate interconnection network simulator. Originally developed for and introduced with the Principles and Practices of Interconnection Networks book, its functionality has since been continuously extended. The current major release, BookSim 2.0, supports a wide range of topologies such as mesh, torus and flattened butterfly networks, provides diverse routing algorithms and includes numerous options for customizing the network’s router microarchitecture.
OptiSystem is a system level simulator based on realistic modeling of fiber-optic communication systems. It possesses a good new simulation environment and a truly hierarchical definition of components and systems. A Graphical User Interface controls the optical component layout and netlist, component models, and presentation graphics. An extensive library of active and passive components includes realistic, wavelength-dependent parameters.
OptiBPM simulator is the computer-aided design software tool enabling the design of complex optical waveguides, which perform guiding, coupling, switching, splitting, multiplexing, and demultiplexing of optical signals in photonic devices. Based on the Beam Propagation Method (BPM) of simulating light passage through any waveguide medium, OptiBPM allows designers to observe computer-simulated light field distribution and examine the radiation and the guided field simultaneously. Reliably characterizing the beam facilitates computer-aided design of a variety of integrated and fiber optic guided wave problems.
RSIM simulator simulates shared-memory multiprocessors (and uniprocessors) built from processors that aggressively exploit instruction-level parallelism (ILP). RSIM is execution-driven and models state-of-the-art ILP processors, an aggressive memory system, and a multiprocessor coherence protocol and interconnect, including contention at all resources.
Processor simulation features include multiple instruction issue, out-of-order scheduling, register renaming, static and dynamic branch prediction, non-blocking loads and stores, speculative load execution before prior stores are disambiguated and optimized memory consistency implementations. Memory simulation features include two-level cache, hierarchy, multiported and pipelined L1 cache, pipelined L2 cache, multiple outstanding cache requests, memory interleaving and software-controlled non-binding prefetching. Multiprocessor system features include cc-NUMA shared-memory system with directory-based coherence, support for MSI or MESI cache coherence protocols, support for sequential consistency, processor consistency, and release consistency and wormhole-routed mesh network.
A general-purpose interconnection network simulator implemented as an extension of YACSIM.
GEM5 is a cycle accurate simulator capable of simulating a Network-on-Chip (NoC). It is an open source simulator written predominantly in C++. The simulator has the capability to simulate cores with different instruction set architectures (ISA) and NoC with different topologies.
A Detailed Interconnection Network Model inside a Full-system Simulation Framework. Garnet is a detailed network model incorporated inside a full-system simulation framework (GEMS) which enables system level performance and power modeling of the interconnection network. Garnet uses Simics from Virtutech for functional simulation.
Task Graphs For Free (TGFF) was designed to provide a flexible and standard way of generating pseudo-random task graphs for use in scheduling and allocation research. This includes the areas of embedded systems, hardware/software co-design, operating systems (both real-time and general-purpose), parallel or distributed hardware or software studies, flow-shop scheduling, as well as any other area which requires problem instances consisting of partially-ordered or directed acyclic graphs (DAGs) of tasks, i.e., task-graphs… Download page
- Website: http://www.fabkura.org/
- Training lectures:
- IEICE (Institute of Electronics, Information and Communication Engineers)
- IPSJ Information Processing Society of Japan
Available FPGA Boards @ ASL
- Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit (P_on_Sept.2017)
- DSP Development Kit, Stratix® III Edition
- Embedded Systems Development Kit, Cyclone® III Edition
- Altera DE2
- EEE Transactions on Emerging Topics in Computing
- Special Issue on Reliability-aware Design and Analysis Methods for Digital Systems: from Gate to System Level Submission deadline: March 1, 2017. View PDF.
- IEEE Transactions on Multi-Scale Computing Systems
- IEICE special issues
- MICRO Abstracts due: March 28th, 2017. Papers due: April 4th, 2017.
- UoA Major Jnl
- Conference Management, etc., Japan
- LINKS: AY Calendar, Forms, ISTC (Wifi) , W Key, AdmSys, ML, GSProfs., CED, APT, Phone#, ASL, U-Ranking;TR, i3eMicro,PARCO,SUP, JPDC,i3eNetwork,Computing,GCitation, JPNconf,AR; University of Aizu Academic Repository, @NITT, Artificial Life and Robotics, JSPS; ACM, RA/TA Form, RA/TA J-Form ,Update Page, UoADATAIN, ML 2016, ACO 2016, Annual Review Editing Support System, UoA Standing Committees; Acronym , HiPEAC, Annual review & Achievements report;;PASSWD CHANGE ; e-Rad ; ; new period system ; IEEE Access; Installing MS Office; Installing Windows