HIGH-PERFORMANCE RELIABLE INTERCONNECT TECHNOLOGIES FOR NOCS AND COGNITIVE SOCS

Current Research Members:  Prof. Ben Abdallah Abderaezk; M2 Akihito Kajikawa

 


Future generations of high-performance computing systems would contain hundreds of components made of processing cores, DSPs, memory, accelerators, learning circuits, FPGAs, etc., all integrated into a single die area of just a few square millimeters. Such a ”tinny” and complex system would be interconnected via a novel on-chip interconnect closer to a sophisticated network than to current bus-based solutions. The on-chip network must provide high-throughput, and low-latency  supports while keeping the area and power consumption low. Moreover, these muti-/many core systems are becoming susceptible to a variety of faults caused by crosstalk, the impact of radiations, oxide breakdown, and so on. As a result, a simple failure in a single transistor caused by one of these factors may compromise the entire system’s dependability where a failure can be illustrated in corrupted message delivery, time requirement unsatisfactory, or even sometimes the whole system collapse.
Our research effort in this area is about solving several design challenges to enable the packet-switched and other novel switching schemes for networks of massively parallel cores. We are currently investigating the following topics: Low-power interconnects for an event-driven large network of neuromorphic cores; Implementation techniques for TSV based NoCs; 3D-IC integration; Fault-tolerant and reliability issues; New topologies and flow-control methods; Photonic Interconnects.


SP4: Fault-tolerant Scalable 3D-NoC (OASIS-2)

Future System-on-Chip (SoC) will contain hundreds of components made of processor cores, DSPs, memory, accelerators, and I/O all integrated into a single die area of just a few square millimeters. Such complex system/SoC will be interconnected via a novel on-chip interconnect closer to a sophisticated network than to current bus-based solutions.This network must provide high throughput and low latency while keeping area and power consumption low.
Our research effort is about solving several design challenges to enable such new paradigm in massively parallel many-core systems. In particular, we are investigating fault-tolerance, 3D-TSV integration, photonic communication, low-power mapping techniques, low-latency adaptive routing. Currently, we are also trying to port the outcome of this new technology to our other ongoing research project about spiking neuro-inspired chips.


SP3: Fault-resilient Photonic On-chip Network for Reliable Many-core SoCs (FT-PHENIC)

Typical electronic Networks-on-Chip (NoCs) are reaching their performance limitations thanks to various factors. One highly sought after the technology is Photonic Networks-on-Chip (PNoCs). PNoCs offer several bene ts over conventional electrical NoCs, such as high-bandwidth support, distance-independent power consumption, lower latency, and improved performance-per-watt. Wavelength Division Multiplexing allows for multiple parallel optical streams of data to concurrently transfer through a single waveguide and MRs can be switched at speeds as high as 40 GHz to realize wavelength-selective modulators or switches. These technologies allow for multiple bits of data to travel concurrently through the same waveguide, which contradicts the one bit per wire limitation of electronic circuits. Another bene t is that data is transferred in an end-to-end fashion once a path is con figured, meaning that the data does not need to be buffered multiple times, and thus saving power. The photonic domain is immune to transient faults caused by radiation but is still susceptible to process variation (PV) and thermal variation (TV) as well as aging. The aging typically occurs faster inactive components as well as elements that have high thermal variation. In the optical domain, faults can occur in MRs, waveguides, routers, etc. Active components, such as photodetectors, have higher failure rates than passive components, e.g. waveguides. Moreover, when paired with the fact that a PNoC is highly vulnerable, as a fault may expose the single-point failure, a faulty MR can cause a message to misdelivered or lost. In this dissertation, a set of novel photonic routing algorithms and architectures are proposed for future on-chip optical networks.

  • Michael Meyer, Micro-ring Fault-resilient Photonic On-chip Network for Reliable High-performance  Many-core Systems-on-Chip”, Ph.D. Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, March 2017.
  • Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”SAFT-PHENIC: a thermal-aware microring fault-resilient photonic NoC”,  The Journal of Supercomputing, June 2018 (in press) [LocalOnly]
  • Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”Microring Fault-resilient Photonic Network-on-Chip for Reliable High-performance Many-core Systems”, Journal of Supercomputing, Volume 73, Issue 4, pp 1567–1599, April 2017.doi: 10.1007/s11227-016-1846-0.
  • Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”Microring Fault-resilient Photonic Network-on-Chip for Reliable High-performance Many-core Systems”, Journal of Supercomputing, Volume 73, Issue 4, pp 1567–1599, April 2017.doi: 10.1007/s11227-016-1846-0.
  • Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, A Power Estimation Method for Mesh-based Photonic NoC Routing Algorithms, IEEE Proc. of the Fourth International Symposium on Computing and Networking, Hiroshima, Japan, November 22-25, 2016.
  • Michael Meyer, Akram Ben Ahmed, Yuki Tanaka, Abderazek Ben Abdallah, “On the Design of a Fault-tolerant Photonic Network-on-Chip”, Proc. of IEEE International Conference on Systems, Man, and Cybernetics (SMC2015), Oct. 9-12, 2015, pp. 821 – 826
  • Michael Meyer, Akram Ben Ahmed, Yuichi Okuyama, Abderazek Ben Abdallah, ”FTTDOR: Microring Fault-resilient Optical Router for Reliable Network-on-Chip Systems”, Proc. of IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs? (MCSoC-15),pp. 227 – 234,Sep 23-25, 2015. (PAPER)
  • Michael Meyer, Abderazek Ben Abdallah, ”Fault-tolerant Photonic Network-on-Chip”, Book Chapter, River Publishers, 2017.
  • Michael Conrad Meyer, Akram Ben Ahmed, Yuki Tanaka, Abderazek Ben Abdallah, “On the Design of a Fault-tolerant Photonic Network-on-Chip”, Proc. of the IEEE International Conference on Systems, Man, and Cybernetics (SMC2015), Oct. 9-12, 2015. (PAPER)

SP2: Si-Photonics Network-on-Chip (PHENIC)

The huge computing power of multi-processor systems would require very large on-chip and off-chip data transfer rates (> 100TB/s). One efficient technology for transmitting this level of information is the photonics interconnects, which promise significant advantages over their electronic counterparts. In particular, nanophotonics (light on the nanometer scale on nanometer-scale devices) on-chip interconnects offer a potentially disruptive technology solution with fundamentally low power dissipation, ultra-high bandwidth, and low latency. Also, when combined with 3D integration technology, photonics interconnect offers advantages over electronic 2D NoC design, such as shorter wire length, higher packing density, and smaller footprint. Moreover, to ensure that these complex systems can accommodate faults and maintain operation, there is a need for the development of an efficient mechanism that can self-detect, self-diagnosis and self-recover in the processing cores as well as in the on-chip interconnect (NOC). The goal of this project is to study new photonic interconnect solutions to improve energy efficiency, and bandwidth of on-chip interconnects for embedded and high-performance many-core systems.


SP1: Scalable Packet-Switched Network-on-Chip (OASIS-1) 

Future embedded and general-purpose processors will be implemented as multicore systems with nanoscale technology consisting of hundreds of processing and storage elements. These multicore systems are emerging as a key design solution for today’s nanoelectronics design problems. The interconnection structure supporting such systems will be closer to a sophisticated network than to current bus-based solutions. Such network must provide higoasis.pngh throughput and low latency while keeping area and power consumption low. Our research efforts is about solving several design challenges to enable such new paradigm in Multicore Systems. In particular, we investigated implementation techniques for basic building blocks, new topologies, flow control techniques, and low-latency, high-throughput/fault-tolerant routing algorithms.

  • A. Ben Ahmed, ”High-throughput Architecture and Routing Algorithms Towards the Design of Reliable Mesh-based Many-Core Network-on-Chip Systems”, Ph.D.Thesis, Graduate School of Computer Science and Engineering, University of Aizu, March 2015. [Thesis.pdf], [slides.pdf]
  • Akram Ben Ahmed, Abderazek Ben Abdallah, “Adaptive fault-tolerant architecture and routing algorithm for reliable many-core 3D-NoC systems“, Journal of Parallel and Distributed Computing, Volumes 93–94, July 2016, Pages 30-43, ISSN 0743-7315, doi:10.1016/j.jpdc.2016.03.014. [preprint.pdf], [BibTex]
  • Akram Ben Ahmed, A. Ben Abdallah, Graceful Deadlock-Free Fault-Tolerant Routing Algorithm for 3D Network-on-Chip Architectures, Journal of Parallel and Distributed Computing 74/4 (2014), pp. 2229-2240 [DOI], [BibTex]
  • A. Ben Ahmed, M. Meyer, Y. Okuyama, and A. Ben Abdallah, ”Adaptive Error- and Traffic Aware Router Architecture for 3D Network-on-Chip Systems”, IEEE Proceedings of the 8th International Symposium on Embedded Multicore/Many-core SoCs (MCSoC-14), pp. 197-2014, Sept. 2014.
  • A. Ben Ahmed, A. Ben Abdallah, OASIS 3D-Router Hardware Physical Design, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, July 8, 2014.
  • A. Ben Ahmed, M. Meyer, Y. Okuyama, and A. Ben Abdallah, Adaptive Error- and Traffic Aware Router Architecture for 3D Network-on-Chip Systems, IEEE Proceedings of the 8th International Symposium on Embedded Multicore/Many-core SoCs (MCSoC-14), pp. 197-204, Sept. 2014. [DOI], [slides.pdf]
  • Akram Ben Ahmed, Achraf Ben Ahmed, A. Ben Abdallah, Deadlock Recovery Support for Fault-tolerant Routing Algorithms in 3D-NoC Architectures”, IEEE Proceedings of the 7th International Symposium on Embedded Multicore/Many-core SoCs (MCSoC-13), pp. 1-6, 2013. [DOI] , [slides.pdf]
  • Akram Ben Ahmed, A. Ben Abdallah, ‘Architecture and Design of High-throughput, Low-latency and Fault-Tolerant Routing Algorithm for 3D-Network-on-Chip”, The Jnl. of Supercomputing, December 2013, Volume 66, Issue 3, pp 1507-1532. [DOI]
  • Akram Ben Ahmed, T. Ouchi, S. Miura, A. Ben Abdallah, ‘Run-Time Monitoring Mechanism for Efficient Design of Application-specific NoC Architectures in Multi/Manycore Era”, IEEE Proc. of the 6th International Workshop on Engineering Parallel and Multicore Systems (ePaMuS2013′), July 2013. [DOI]
  • Akram Ben Ahmed, A. Ben Abdallah, ‘Low-overhead Routing Algorithm for 3D Network-on-Chip‘, IEEE Proc. of The Third International Conference on Networking and Computing (ICNC’12), pp. 23-32, 2012. [DOI]
  • Akram Ben Ahmed, A. Ben Abdallah, LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture, IEEE Proceedings of the 6th International Symposium on Embedded Multicore SoCs (MCSoC-12), pp. 167-174, 2012. [DOI]
  • Akram Ben Ahmed, A. Ben Abdallah, ONoC-SPL Customized Network-on-Chip (NoC) Architecture and Prototyping for Data-intensive Computation Applications”, IEEE Proceedings of The 4th International Conference on Awareness Science and Technology, pp. 257-262, 2012. DOI
  • A. Ben Ahmed, A. Ben Abdallah, K. Kuroda, Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC”, IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), pp.67-73, Nov. 2010. (best paper award) (slides.pdf), (paper.pdf)
  • K. Mori, A. Esch, A. Ben Abdallah, K. Kuroda, ”Advanced Design Issues for OASIS Network-on-Chip Architecture”, IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010),pp.74-79, Nov. 2010. (slides.pdf); (paper.pdf)
  • Shohei Miura, Abderazek Ben Abdallah, Kenichi Kuroda, parameterizable are suitable for the generation of design space exploration and MCSoC NoC hardware design and pre-evaluation of (PNoC), 34th Parthenon Study Group, pp.105-108. Aug. 2009. (slides.pdf)
  • Shohei Miura, Abderazek Ben Abdallah, Kenichi Kuroda, PNoC: Design and Preliminary Evaluation of a Parameterizable NoC for MCSoC Generation and Design Space Exploration‘, The 19th Intelligent System Symposium (FAN 2009), pp.314-317, Sep.2009. (slides.pdf)
  • Kenichi Mori, Abderazek Ben Abdallah, Kenichi Kuroda, Design and Evaluation of a Complexity-Effective Network-on-Chip Architecture on FPGA, The 19th Intelligent System Symposium (FAN 2009), pp.318-321, Sep. 2009. (slides.pdf)
  • A. Ben Abdallah, T. Yoshinaga and M. Sowa, “Mathematical Model for Multiobjective Synthesis of NoC Architectures,” IEEE Proc. of the 36th International Conference on Parallel Processing, Sept. 4-8, 2007. (paper.pdf)
  • A. Ben Abdallah, Masahiro Sowa, Basic Network-on-Chip Interconnection for Future Gigascale MCSoCs Applications: Communication and Computation Orthogonalization‘, Proc. of the Symposium on Science, Society, and Technology (TJASSST2006), pp. 1-7, 2006/12
  • Traffic Pattern Testbench: (source_code.zip).

Completed Research Topics & Theses

  • Micro-ring Fault-resilient Photonic On-chip Network for Reliable High-performance Many-core Systems-on-Chip
  • Reliable Real-time Multi-core Vision System-on-Chip based on OASIS NoC
  • High-performance, Scalable Photonics On-chip Network for Many-core Systems-on-Chip
  • Evaluation of Error Detection Mechanism for 3D-OASIS-Network-on-Chip System,
  • Design and Analysis of Electrical Control Router for Hybrid Photonics NoC System
  • Power and Performance Comparison of Electronic 2D-NoC and Opto-Electronic 2D-NoC,
  • High-throughput Architecture and Routing Algorithms Towards the Design of Reliable Mesh-based Many-Core Network-on-Chip Systems,
  • Architecture and Design of an Efficient Router for OASIS 3D Network-on-Chip System,
  • Design and Evaluation of Efficient Error Detection Mechanism for OASIS 3D-NoC
  • Hardware Prototyping and Evaluation of Distributed Routing Core Network-Interface for OASIS NoC Architecture
  • OASIS Network-on-Chip Prototyping on FPGA
  • On the Design of a 3D Network-on-Chip for Many-core SoC
  • Design of Parametrizable Network-on-Chip
  • Architecture and Design of Core Network Interface for Distributed Routing in OASIS NoC
  • OASIS NoC Topology Optimization with ShortPath Link
  • Shared Memory MultiQueueCore Processor Design’
  • Multicore SoC Architecture for Real-time Data Intensive ECG Processing
  • Development Environment for Single Chip Computer intended for Queue Computing Development and Education
  • Architecture and Design of Application Specific Multicore SoC
  • Development of User-Friendly Assembler for Queue Computers
  • Optimizations Techniques and FPGA Prototyping of OASIS Network-on-Chip

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