Neuro-inspired Hardware

NASH: Neuro-inspired ArchitectureS in Hardware 

Hardware implementations of spiking neural network systems are efficient and effective methods to provide cognitive functions on a chip compared with the conventional stored-program computing style. The challenges that need to be solved toward building such a neuro-inspired computing paradigm with a massive number of synapses include building a small-size massively parallel architecture with low-power consumption, efficient neuro-coding schemes, and lightweight on-chip learning algorithms. In addition, traditional direct neuron-to-neuron interconnection based on a shared-bus is not scalable. Therefore, the above constraints make the deployment of neuro-inspired (brain-like) IC a challenging on-chip interconnect problem, where a balance between scalability and biological real-time requirements needs to be achieved.
Our goal in this project is to research and develop an ultra-low-power neuro-inspired spiking massively multicore Chip/SoC based on new deep neuronal algorithms and scalable reconfigurable interconnects. We are researching and developing FPGA and ASIC Chips/SoCs for vision and learning in adaptive autonomous vehicles and mobile land/aerial robots. We are also exploring innovative hardware (i.e., memristor) based low-power circuits for learning on-chip.

On-going sub-research topics

  • Memristor Spike-based Deep Learning & Stochastic Spiking in Large-scale Neuro-inspired Chip
  • Reconfigurable Neuromorphic Synapse On-chip Interconnect.

Related Publications

  • The H. Vu, Yuichi Okuyama, Abderazek Ben Abdallah, ‘’Fault-tolerant Reconfigurable Synapse On-chip Interconnect for Neuromorphic Systems’’, IEEE Transactions on Emerging Topics in Computing, TBS, May 2018.
  • Abderazek Ben Abdallah, Keynote Speech, 2018 International Conference on Intelligent Autonomous Systems (ICoIAS’2018), March 1-3, 2018, Singapore. Title: ”Neuro-inspired Computing Systems & Applications.” [slides.pdf]
  • The H. Vu, Ryunosuke Murakami, Yuichi Okuyama, Abderazek Ben Abdallah, ”Efficient Optimization and Hardware Acceleration of CNNs towards the Design of a Scalable Neuro-inspired Architecture in Hardware”, IEEE International Conference on Big Data and Smart Computing (BigComp-2018), January 15-18, 2018. [slides.pdf]
  • Kanta Suzuki, Yuichi Okuyama, Abderazek Ben, Abdallah, ”Hardware Design of a Leaky Integrate and Fire Neuron Core Towards the Design of a Low-power Neuro-inspired Spike-based Multicore SoC”, Information Processing Society Tohoku Branch Conference, Feb. 10, 2018. [slides.pdf]
  • Ryunosuke Murakami, Yuichi Okuyama, Abderazek Ben Abdallah, ”Animal Recognition and Identification with Deep Convolutional Neural Networks for Farm Monitoring”, Information Processing Society Tohoku Branch Conference, Feb. 10, 2018. [slides.pdf]
  • Yuji Murakami, Yuichi Okuyama, Abderazek Ben Abdallah, ”SRAM Based Neural Network System for Traffic-Light Recognition in Autonomous Vehicles”, Information Processing Society Tohoku Branch Conference, Feb. 10, 2018.  [slides.pdf]

OASIS-2: Fault-tolerant Scalable On-chip Interconnects

Future System-on-Chip (SoC) will contain hundreds of components made of processor cores, DSPs, memory, accelerators, and I/O all integrated into a single die area of just a few square millimeters. Such complex system/SoC will be interconnected via a novel on-chip interconnect closer to a sophisticated network than to current bus-based solutions.This network must provide high throughput and low latency while keeping area and power consumption low.
Our research effort is about solving several design challenges to enable such new paradigm in massively parallel many-core systems. In particular, we are investigating fault-tolerance, 3D-TSV integration, photonic communication, low-power mapping techniques, low-latency adaptive routing. Our recent current target application is adaptive neuro-inspired chips.

Related Publications

 

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