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Nam Khanh Dang, Ph.D. Student

Biography

I am currently a Ph.D. candidate at the Adaptive Systems Laboratory, the University of Aizu. I  received a B.Sc. degree in Electronics – Telecommunication technology from Vietnam National University (VNU) of Engineering and Technology in 2011 and an M.Sc. degree in Information, Systems, and Technology from the University of Paris-Sud XI in 2013. My research interests include System-on-Chips/Network-on-Chips, 3D Integrations, and fault-tolerant systems.

Publications

  1. Khanh N. Dang, Akram Ben Ahmed, Xuan-Tu Tran, Yuichi Okuyama and Abderazek Ben Abdallah, ”A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model”, IEEE Transactions on Very Large Scale Integration Systems (TVLSI),  doi10.1109/TVLSI.2017.2736004. [MAJOR]
  2. Khanh N. Dang, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”A Low-overhead Soft-Hard Fault Tolerant Architecture, Design and Management Scheme for Reliable High-performance Many-core 3D-NoC Systems”, Journal of Supercomputing, Volume 73, Issue 6, pp 2705–2729, 2017. doi:10.1007/s11227-016-1951-0  [MAJOR]
  3. Khanh N. Dang, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, Reliability Assessment and Quantitative Evaluation of Soft-Error Resilient 3D NoC System, 25th IEEE Asian Test Symposium (ATS’16), November 21-24, 2016. [MAJOR]
  4. Khanh N. Dang, Yuichi Okuyama, Abderazek Ben Abdallah, ”Soft-Error Resilient Network-on-Chip for Safety-Critical Applications”, 2016 IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), June 27 – 29, 2016. [MAJOR]
  5. Khanh N. Dang, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, Xuan-Tu Tran, “Soft-Error Resilient 3D Network-on-Chip Router“, Proc. of IEEE 7th International Conference on Awareness Science and Technology (iCAST 2015), pp. 84 – 90, Sep. 22-24, 2015. [MAJOR]

Submitted or Under Submission

  • Khanh N. Dang,  Akram Ben Ahmed, Yuichi Okuyama, and Abderazek Ben Abdallah, ”Scalable design methodology and online algorithm for TSV-cluster defects recovery in highly reliable 3D-NoC systems”, Submitted to the  IEEE Transactions on Emerging Topics in Computing, Special Issue on Reliability-aware Design and Analysis Methods for Digital Systems: from Gate to System Level, March 1st, 2017.

Research (internal)

Thesis

  • Development of On-Chip Communication Fault-Resilient Adaptive Architectures and Algorithms for 3D-IC Technologies (3次元IC技術のための適応型耐障害チップ内通信アーキテクチャとアルゴリズムの開発)

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