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Recent Projects

PHENIC: Photonic Network-on-Chip (2014-2016)

The huge computing power of multi-processor systems would require very large on-chip and off-chip data transfer rates (> 100TB/s). One efficient technology for transmitting this level of information is the photonics interconnects, which promise significant advantages over their electronic counterparts. In particular, nanophotonics (light on the nanometer scale on nanometer-scale devices) on-chip interconnects offer a potentially disruptive technology solution with fundamentally low power dissipation, ultra-high bandwidth, and low latency. Also, when combined with 3D integration technology, photonics interconnect offers advantages over electronic 2D NoC design, such as shorter wire length, higher packing density, and smaller footprint. Moreover, to ensure that these complex systems can accommodate faults and maintain operation, there is a need for the development of an efficient mechanism that can self-detect, self-diagnosis and self-recover in the processing cores as well as in the on-chip interconnect (NOC).

The goal of this project is to study new photonic interconnect solutions to improve energy efficiency, and bandwidth of on-chip interconnects for embedded and high-performance many-core systems.

Related Publications

  • Michael Meyer, Micro-ring Fault-resilient Photonic On-chip Network for Reliable High-performance Many-core Systems-on-Chip, Ph.D. Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, March 2017.
  • Achraf Ben Ahmed, ‘High-performance Scalable Photonics On-chip Network for Many-core Systems-on-Chip”, Ph.D. Thesis, GraduteSchool of Computer Science and Engineering, The University of Aizu, March 2016
  • Achraf  Ben Ahmed, Tsutomu Yoshinaga, Abderazek Ben Abdallah, “Scalable Photonic Networks-on-Chip Architecture Based on a Novel Wavelength-Shifting Mechanism”, IEEE Transactions on Emerging Topics in Computing, 2017. DOI: 10.1109/TETC.2017.2737016
  • Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah,Microring Fault-resilient Photonic Network-on-Chip for Reliable High-performance Many-core Systems, Journal of Supercomputing, Volume 73, Issue 4, pp 1567–1599, April 2017.doi: 10.1007/s11227-016-1846-0.
  • Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”A Thermal-aware Microring Fault-resilient Electro-Photonic NoC for High-bandwidth Manycore Systems”, submitted to the IEEE Transactions on Multi-Scale Computing Systems, April 10, 2017.
  • Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, Microring Fault-resilient Photonic Network-on-Chip for Reliable High-performance Many-core Systems, Journal of Supercomputing, Volume 73, Issue 4, pp 1567–1599, April 2017.doi: 10.1007/s11227-016-1846-0.
  • Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, A Power Estimation Method for Mesh-based Photonic NoC Routing Algorithms, IEEE Proc. of the Fourth International Symposium on Computing and Networking, Hiroshima, Japan, November 22-25, 2016.
  • Michael Meyer, Akram Ben Ahmed, Yuki Tanaka, Abderazek Ben Abdallah, “On the Design of a Fault-tolerant Photonic Network-on-Chip”, Proc. of IEEE International Conference on Systems, Man, and Cybernetics (SMC2015), Oct. 9-12, 2015, pp. 821 – 826
  • Michael Meyer, Akram Ben Ahmed, Yuichi Okuyama, Abderazek Ben Abdallah, ”FTTDOR: Microring Fault-resilient Optical Router for Reliable Network-on-Chip Systems”, Proc. of IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs? (MCSoC-15),pp. 227 – 234,Sep 23-25, 2015.
  • Michael Meyer, Abderazek Ben Abdallah, ”Fault-tolerant Photonic Network-on-Chip”, Book Chapter, River Publishers, 2017 (.pdf})
  • Achraf Ben Ahmed, Abderazek Ben Abdallah, ”An Energy-efficient High-throughput Mesh-based Phototonic On-chip Interconnect for Many-core Systems”, Photonics, 2016; 3(2):15. doi:10.3390/photonics3020015. [paper.pdf], [BibTex?]
  • Achraf Ben Ahmed, A. Ben Abdallah, “Hybrid Silicon-Photonic Network-on-Chip for Future Generations of High-performance Many-core Systems”, Journal of Supercomputing, 2015. DOI: 10.1007/s11227-015-1539-0.
  • Achraf Ben Ahmed, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, Hybrid Photonic NoC based on Non-blocking Photonic Switch and Light-weight Electronic Router, Proc. of the IEEE International Conference on Systems, Man, and Cybernetics (SMC2015), Oct. 9-12, 2015. (PAPER)
  • Achraf Ben Ahmed, Yuichi Okuyama, Abderazek Ben Abdallah, Contention-free Routing for Hybrid Photonic Mesh-based Network-on-Chip Systems, Proc. of 9th IEEE International Symposium on Embedded Multicore/Manycore SoCs? (MCSoC-15), Sept. 2015. (PAPER)
  • Michael Meyer, Akram Ben Ahmed, Yuichi Okuyama, Abderazek Ben Abdallah, Microring Fault-resilient Optical Router for Reliable Network-on-Chip Systems, Proc. of 9th IEEE International Symposium on Embedded Multicore/Manycore SoCs? (MCSoC-15), Sept. 2015. (PAPER)
  • Michael Conrad Meyer, Akram Ben Ahmed, Yuki Tanaka, Abderazek Ben Abdallah, “On the Design of a Fault-tolerant Photonic Network-on-Chip”, Proc. of the IEEE International Conference on Systems, Man, and Cybernetics (SMC2015), Oct. 9-12, 2015. (PAPER)
  • A.Ben Ahmed, Y.Okuyama, A.Ben Abdallah, “Non-blocking Electro-optic Network-on-Chip Router for High-throughput and Low-power Many-core Systems”, accepted for publication in The World Congress on Information Technology and Computer Applications 2015, Hammamet, Tunisia, June 11-13, 2015 (PDF), (Slides)
  • A.Ben Ahmed, M.Meyer, Y.Okuyama, A.Ben Abdallah, “Efficient Router Architecture, Design and Performance Exploration for Many-core Hybrid Photonic Network-on-Chip (2D-PHENIC)”, accepted for publication in the 2015 International Conference on Information Science and Control Engineering ICISCE 2015, Shanghai, China, April 24-26, 2015 (PDF)
  • Achraf Ben Ahmed, A. Ben Abdallah, PHENIC: Towards Photonic 3D-Network-on-Chip Architecture for High-throughput Many-core Systems-on-Chip, IEEE Proceedings of the 14th International conference on Sciences and Techniques of Automatic control and computer engineering, Dec. 2013. DOI
  • Achraf Ben Ahmed, A. Ben Abdallah, Hardware/Software Prototyping of Dependable Real-Time System for Elderly Health Monitoring, IEEE Proc. of the World Congress on Computer and IT, ICMAES, June 2013. [DOI]
  • Achraf Ben Ahmed, Yumiko Kimezawa, A. Ben Abdallah, Towards Smart Health Monitoring System for Elderly People, IEEE Proceedings of The 4th International Conference on Awareness Science and Technology, pp. 248-253, 2012. [DOI]
  • Achraf Ben Ahmed, PHENIC Design-Flow Poster, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu}, January 18, 2016.
  • A. Ben Abdallah, On-Chip Optical Interconnects: Prospects and Challenges, Invited Talk, 6th International Conference on Soft Computing and Pattern Recognition, August 11-14, 2014
  • A. Ben Abdallah, Si-Photonics Technology Towards femtoJoule/bit Optical Communication in Many-core Chips (STA2014), Invited Talk, 15th International conference on Sciences and Techniques of Automatic control & Computer Engineering, Dec. 21-23, 2014.
  • A. Ben Abdallah, Silicon Photonic 3D-Network-on-Chip Architecture for High-performance Heterogeneous Manycore System-on-Chip, Ver. 1.1, Technical Report, September 1, 2013.
  • A. Ben Abdallah, Silicon Photonic 3D-Network-on-Chip Architecture for High-performance Heterogeneous Manycore System-on-Chip, Ver.1.0, Technical Report, July 15, 2013.

OASIS-1: Scalable Packet-Switched Network-on-Chip (2011-2013)

Future embedded and general-purpose processors will be implemented as multicore systems with nanoscale technology consisting of hundreds of processing and storage elements. These multicore systems are emerging as a key design solution for today’s nanoelectronics design problems. The interconnection structure supporting such systems will be closer to a sophisticated network than to current bus-based solutions. Such network must provide higoasis.pngh throughput and low latency while keeping area and power consumption low. Our research efforts is about solving several design challenges to enable such new paradigm in Multicore Systems. In particular, we investigated implementation techniques for basic building blocks, new topologies, flow control techniques, and low-latency, high-throughput/fault-tolerant routing algorithms.

Related Publications

  • Khanh N. Dang, Akram Ben Ahmed, Xuan-Tu Tran, Yuichi Okuyama, Abderazek Ben Abdallah, ”A Comprehensive Reliability Assessment of Fault-Resilient Network-on-Chip Using Analytical Model”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017. DOI: 10.1109/TVLSI.2017.2736004
  • A. Ben Ahmed, ”High-throughput Architecture and Routing Algorithms Towards the Design of Reliable Mesh-based Many-Core Network-on-Chip Systems”, Ph.D. Thesis, Graduate School of Computer Science and Engineering, University of Aizu, March 2015. [Thesis.pdf], [slides.pdf]
  • Akram Ben Ahmed, Abderazek Ben Abdallah, “Adaptive fault-tolerant architecture and routing algorithm for reliable many-core 3D-NoC systems“, Journal of Parallel and Distributed Computing, Volumes 93–94, July 2016, Pages 30-43, ISSN 0743-7315, doi:10.1016/j.jpdc.2016.03.014. [preprint.pdf], [BibTex]
  • Akram Ben Ahmed, A. Ben Abdallah, Graceful Deadlock-Free Fault-Tolerant Routing Algorithm for 3D Network-on-Chip Architectures, Journal of Parallel and Distributed Computing 74/4 (2014), pp. 2229-2240 [DOI], [BibTex]
  • A. Ben Ahmed, M. Meyer, Y. Okuyama, and A. Ben Abdallah, ”Adaptive Error- and Traffic Aware Router Architecture for 3D Network-on-Chip Systems”, IEEE Proceedings of the 8th International Symposium on Embedded Multicore/Many-core SoCs (MCSoC-14), pp. 197-2014, Sept. 2014.
  • A. Ben Ahmed, A. Ben Abdallah, OASIS 3D-Router Hardware Physical Design, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, July 8, 2014.
  • A. Ben Ahmed, M. Meyer, Y. Okuyama, and A. Ben Abdallah, Adaptive Error- and Traffic Aware Router Architecture for 3D Network-on-Chip Systems, IEEE Proceedings of the 8th International Symposium on Embedded Multicore/Many-core SoCs (MCSoC-14), pp. 197-204, Sept. 2014. [DOI], [slides.pdf]
  • Akram Ben Ahmed, Achraf Ben Ahmed, A. Ben Abdallah, Deadlock Recovery Support for Fault-tolerant Routing Algorithms in 3D-NoC Architectures”, IEEE Proceedings of the 7th International Symposium on Embedded Multicore/Many-core SoCs (MCSoC-13), pp. 1-6, 2013. [DOI] , [slides.pdf]
  • Akram Ben Ahmed, A. Ben Abdallah, ‘Architecture and Design of High-throughput, Low-latency and Fault-Tolerant Routing Algorithm for 3D-Network-on-Chip”, The Jnl. of Supercomputing, December 2013, Volume 66, Issue 3, pp 1507-1532. [DOI]
  • Akram Ben Ahmed, T. Ouchi, S. Miura, A. Ben Abdallah, ‘Run-Time Monitoring Mechanism for Efficient Design of Application-specific NoC Architectures in Multi/Manycore Era”, IEEE Proc. of the 6th International Workshop on Engineering Parallel and Multicore Systems (ePaMuS2013′), July 2013. [DOI]
  • Akram Ben Ahmed, A. Ben Abdallah, ‘Low-overhead Routing Algorithm for 3D Network-on-Chip‘, IEEE Proc. of The Third International Conference on Networking and Computing (ICNC’12), pp. 23-32, 2012. [DOI]
  • Akram Ben Ahmed, A. Ben Abdallah, LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture, IEEE Proceedings of the 6th International Symposium on Embedded Multicore SoCs (MCSoC-12), pp. 167-174, 2012. [DOI]
  • Akram Ben Ahmed, A. Ben Abdallah, ONoC-SPL Customized Network-on-Chip (NoC) Architecture and Prototyping for Data-intensive Computation Applications”, IEEE Proceedings of The 4th International Conference on Awareness Science and Technology, pp. 257-262, 2012. DOI
  • A. Ben Ahmed, A. Ben Abdallah, K. Kuroda, Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC”, IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), pp.67-73, Nov. 2010. (best paper award) (slides.pdf), (paper.pdf)
  • K. Mori, A. Esch, A. Ben Abdallah, K. Kuroda, ”Advanced Design Issues for OASIS Network-on-Chip Architecture”, IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010),pp.74-79, Nov. 2010. (slides.pdf); (paper.pdf)
  • Shohei Miura, Abderazek Ben Abdallah, Kenichi Kuroda, parameterizable are suitable for the generation of design space exploration and MCSoC NoC hardware design and pre-evaluation of (PNoC), 34th Parthenon Study Group, pp.105-108. Aug. 2009 . (slides.pdf)
  • Shohei Miura, Abderazek Ben Abdallah, Kenichi Kuroda, PNoC: Design and Preliminary Evaluation of a Parameterizable NoC for MCSoC Generation and Design Space Exploration‘, The 19th Intelligent System Symposium (FAN 2009), pp.314-317, Sep.2009. (slides.pdf)
  • Kenichi Mori, Abderazek Ben Abdallah, Kenichi Kuroda, Design and Evaluation of a Complexity-Effective Network-on-Chip Architecture on FPGA, The 19th Intelligent System Symposium (FAN 2009), pp.318-321, Sep. 2009. (slides.pdf)
  • A. Ben Abdallah, T. Yoshinaga and M. Sowa, “Mathematical Model for Multiobjective Synthesis of NoC Architectures,” IEEE Proc. of the 36th International Conference on Parallel Processing, Sept. 4-8, 2007. (paper.pdf)
  • A. Ben Abdallah, Masahiro Sowa, Basic Network-on-Chip Interconnection for Future Gigascale MCSoCs Applications: Communication and Computation Orthogonalization‘, Proc. of the Symposium on Science, Society, and Technology (TJASSST2006), pp. 1-7, 2006/12
  • Traffic Pattern Testbench: (source_code.zip).

BANSMOM: Dependable Real-Time Multicore System-on-Chip for Elderly Health Monitoring (2008-2010)

Recent technological advances in wireless networking, microelectronics, and the Internet allow us to change fundamentally the way elderly health care services are practiced. Traditionally, embedded personal medical monitoring systems have been used only to collect data. Data processing and analysis are performed off-line, making such devices impractical for continual monitoring and early detection of medical disorders.

The goal of this project is to research about a smart, dependable embedded system to monitor elderly health remotely and in real-time. In particular, we investigate an extreme area in the design space of networked embedded objects: the domain of low energy, and real-time. Issues related to the design, implementation, and deployment of such systems are also studied.

Related Publications

  • Achraf Ben Ahmed, A. Ben Abdallah, ”Interactive Real-time Interface for Smart Remote Health Monitoring and Analysis”, Master’s Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2013 [Thesis.pdf] [Slides.pdf] 
  • Achraf Ben Ahmed, A. Ben Abdallah, ”Architecture and Design of Real-Time Systems for Elderly Health Monitoring”, Jnl of Embedded Systems  [preprint.pdf] (to appear)

Queue Computer (1999-2008)

This project focuses on the research about a novel low power and high-performance parallel processor based on Queue computation model, whqc2ere Queue programs are generated by traversing a given data flow graph using level order traversal. The Queue processor uses a circular queue register to manipulates operands and results and exploits parallelism dynamically with “little efforts” when compared with conventional architectures. The nonexistence of false dependencies allows programs to expose maximum parallelism that the queue processor can execute without complex and power-hungry hardware such as register renaming and large instruction windows.

Parallel processing allows queue processors to speed-up the execution of applications. We are researching and developing a complete tool-chain for this promising computing model consisting of a compiler, assembler, functional and cycle accurate simulator, and hardware design.

Related Publications

  • Hiroki Hoshino, Development of Parallel Queue Processor Architecture and its Integrated Development Environment, Master’s Thesis, The University of Aizu, Feb. 2011. [slides]
  • Masashi Masuda, Produced Order Queue Compiler Design, Mater’s Thesis, The University of Aizu, Feb. 2011. [slides]
  • A. Ben Abdallah, M. Masuda, A. Canedo, K. Kuroda, Natural Instruction Level Parallelism-aware Compiler for High-Performance Processor Architecture, The Journal of Supercomputing, Volume 57, Number 3, pp. 314-338, Sept. 2011.[DOI]
  • A. Canedo, A. Ben Abdallah, and M. Sowa, Efficient Compilation for Queue Size-Constrained Queue Processors, The Journal of Parallel Computing, Vol.35, pp. 213-225, 2009.
  • A. Canedo, A. Ben Abdallah, and M. Sowa, “Compiler Support for Code Size Reduction using a Queue-based Processor,” Tqc3ransactions on High-Performance Embedded Architectures and Compilers, Vol. 2, Issue 4, pp. 269-285, 2009.
  • A. Ben Abdallah, A. Canedo, T. Yoshinaga, and M. Sowa, The QC-2 Parallel Queue Processor Architecture, Journal of Parallel and Distributed Computing, Vol. 68, No. 2, pp. 235-245, 2008.
  • A. Canedo, A. Ben Abdallah, and M. Sowa, “A New Code Generation Algorithm for 2-offset Producer Order Queue Computation Model”, Journal of Computer Languages, Systems & Structures, Vol. 34, Issue 4, pp. 184-194, 2007.
  • A. Ben Abdallah, Sotaro Kawata, and M. Sowa, “Design and Architecture for an Embedded 32-bit QueueCore”, Journal of Embedded Computing, Special Issue in embedded single-chip multicore architectures, Vol. 2, No. 2, pp. 191-205, 2006.
  • A. Ben Abdallah, T. Yoshinaga, and M. Sowa, “High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core,” Journal of Supercomputing, Vol. 38, Number 1, pp. 3-15, 2006
  • M. Masuda, A. Ben Abdallah, A. Canedo, “Software and Hardware Design Issues for Low-Complexity High-Performance Processor Architecture”, The 38th International Conference on Parallel Processing Workshops, pp. 558-565, 2009
  • M. Masuda, A. Canedo, A. Ben Abdallah, “Efficient Code Generation Algorithm for Natural Instruction Level Parallelism-aware Queue Architecture,” The 19th Intelligent System Symposium (FAN 2009), pp.308-313, Sep. 2009.(Best Presentation Award).
  • H. Hoshino, A. Ben Abdallah, and K. Kuroda, “Advanced Optimization and Design Issues of a 32-bit Embedded Processor Based on Produced Order Queue Computation Model”, IEEE/IFIP Int’l Conf. on Embedded and Ubiquitous Computing (EUC2008),pp.16-22, Dec.2008.
  • A. Canedo, A. Ben Abdallah, and M. Sowa, “Quantitative Evaluation of Common Subexpression Elimination on Queue Machines,” Proc. IEEE Int’l Sym. on Parallel Architectures, Algorithms, and Networks (I-SPAN 2008), pp.25-30. 2008.
  • A. Canedo, A. Ben Abdallah, and M. Sowa, “Queue Register File Optimization Algorithm for QueueCore Processor,” Proc. IEEE 19th International Symposium on Computer Architecture and High-Performance Computing (SBAC-PAD 2007), pp. 169-176, 2007.
  • A. Ben Abdallah, Mudar Sarem, and M. Sowa, ”Dynamic Fast Issue Mechanism (DFI) for Dynamic Scheduled Processors”, IEICE transactions on Fundamental of Electronics, Communications, and computer Science, Vol. E83-A No.12 pp.2417-2425, Dec. 2000.

SAP: Self-Adaptive Processor (2000-2007)

This research is a novel computing model and architecture based on an innovative self-adaptation behavior, which will provide scalability, high resource utilization, and high-performance by dynamically synthesizing the right resources composition based on temporal program performance demand(s). A given program is considered as a set of small objects competing with other programs running on the same many-core platform. In this computing model, a given program can dynamically occupy/find new space and spread/migrate its computation (various parallelism levels) to appropriate neighbor cores. Using our dynamic temporal-allocation-technique, a given program can de-allocate resources according to its new performance requirement.

We are investigating novel concepts of run-time and resource-aware programming as well as self-adaptive architecture which evaluates its global behavior and change it when better functionality or performance is possible. The challenge is often to identify how to change specific behaviors to achieve the desired improvement.

Related Publications

  • Taichi Maekawa, Design, and Evaluation of Dual Mode Processor Architecture, Master’s Thesis, The University of Aizu, Feb. 2011.
  • Taichi Maekawa, Abderazek Ben Abdallah, Kenichi Kuroda, Single Instruction Dual-Execution Model Processor Architecture, IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, Shanghai, pp.30-36, Dec. 2008.
  • Mushiq Akanda, A. Ben Abdallah, and M. Sowa, Dual-Execution Mode Processor Architecture for Embedded Applications”, Journal of Mobile Multimedia, Vol. 3, No. 4, pp. 347-370, 2007.
  • Mushfiq Akanda, Abderazek Ben Abdallah, Sowa Masahiro, Dual-Execution Mode Processor Architecture, Journal of Supercomputing, Vol. 44, No. 2, pp. 103-125, 2008.
  • Abderazek Ben Abdallah, Soshi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa, On the Design of Register-Queue Based Processor Architecture (FaRM-rq), Lecture Notes in Computer Science, Springer-Verlag, vol. 2745, pp. 248-262, July 2003.
  • Abderazek Ben Abdallah, Soshi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa, Reduced Bit-Width Instruction Set Architecture for Q-mode Execution in Hybrid Processor Architecture (FaRM-rq), IPSJ SIG TR, pp. 19-23, June 2003.
  • Mushifiq Akanda, Abderazek Ben Abdallah, Masahiro Sowa, Dual-Execution Mode Processor Architecture for Embedded Applications, in Journal of Mobile Multimedia, Vol. 3, No. 4, 2007, pp. 347-370.
  • Abderazek Ben Abdallah, Soshi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa, Complexity Analysis of a Functional Assignment Register Microprocessor, Proc. of the Int. Workshop on Modern Science and Technology, IWMST02, pp.116-123, Sep. 2002.
  • Abderazek Ben Abdallah, Dynamic Instructions Issue Algorithm and a Queue Execution Model Toward the Design of Hybrid Processor Architecture”, Ph.D. thesis, Graduate School of Information Systems, the Univ. of Electro-Communications, March 2002.
  • Abderazek Ben Abdallah, Kirilka Nikolova, Masahiro Sowa, FARM-Queue Mode: On a Practical Queue Execution Model, Proceedings of the Int. Conf. on Circuits and Systems, Computers and Communications, Tokushima, Japan, pp.939-944, July 2001.
  • Abderazek Ben Abdallah, Mudar Sarem, Masahiro Sowa, Dynamic Fast Issue Mechanism (DFI) for Dynamic Scheduled Processors, IEICE Transaction on Fundamental of Electronics, Communications and Computer Science, Vol.E83-A No.12 pp.2417-2425, Dec, 2001
  • Abderazek Ben Abdallah, Kirilka Nikolova Tutomu Yoshinaga, Masahiro Sowa, FARM Queue Mode: On a Practical Queue Execution Model (QEM), TIWSS’2001, October 2001.
  • Abderazek Ben Abdallah, Kirilka Nikolova, Masahiro Sowa, FARM-Queue Execution Model: Towards an Alternative Computing Paradigm, Proceedings of IPSJ Symposium, Yokohama pp.99-100, March 2000
  • Abderazek Ben Abdallah, Mudar Sarem, Masahiro Sowa, Acyclic DFG on a Queue Machine, JSPP2000, Tokyo, Japan, pp.119-120, 2000.
  • Abderazek Ben Abdallah, Mudra Sarem., Masahiro Sowa, Instruction Scheduling System for Super scalar Processors, JSPP2000, Tokyo, Japan, pp.161, Apr. 2000 .
  • Abderazek Ben Abdallah, Masahiro Sowa, DRA: Dynamic Register Allocator Mechanism For FaRM Microprocessor. The 3rd International Workshop on Advanced Parallel Processing Technologies, Changsha, PRC, pp.131-136, Oct. 1999

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