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Current Projects

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Research on Ultra-low Power Spiking Neuro-inspired System 

The biological brain implements parallel computations using a complex structure that is different from the conventional von Neumann or load/store computing style. Our brain is a low-power, fault-tolerant, and high-performance machine! It consumes only about 20W and brain circuits continue to operate as the organism needs even when the circuit (neuron, neuroglia, etc.) is perturbed or died. Hardware implementations of artificial neural networks are efficient and effective methods to provide cognitive functions on a chip compared with conventional von Neumann processors. The challenges that need to be solved toward reaching such a computing system include building a small-size massively parallel architecture with scalable interconnects, low-power consumption, and reliable neuro-inspired computing schemes for implementation of learning in hardware.

Our goal in this project is to research and develop an ultra-low power spiking neuro-inspired system targeted for a new class of applications ranging from IoT devices/agents and brain implants to high-performance computing co-/processing. This new system will be based on new deep neuronal algorithms and circuits for online on-chip adaptation, learning, and high-throughput. Moreover, the system will serve as an adaptive configurable neural network emulation platform with its software environment for systematic parameter explorations.

Research on Fault-tolerant On-chip Communication Networks 

Future System-on-Chip (SoC) will contain hundreds of components made of processor cores, DSPs, memory, accelerators, and I/O all integrated into a single die area of just a few square millimeters. Such small complex SoC will be interconnected via a novel on-chip interconnect closer to a sophisticated network than to current bus-based solutions.This network must provide high throughput and low latency while keeping area and power consumption low. Our research effort is about solving several design challenges to enable such new NoC paradigm in many-core systems. In particular, we are investigating implementation techniques for basic building blocks, new topologies, flow control techniques, and low-latency, high-throughput, and fault-tolerant routing algorithms.

Our research effort is about solving several design challenges to enable such new paradigm in many-core systems. In particular, we are investigating fault-tolerance, TSV integration, 3D-IC technologies, low-power mapping techniques, low-latency adaptive routing, and new applications development.

==> Recent Projects [最近のプロジェクト]

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