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Research on Ultra-low Power Spiking Neuro-inspired Computing System 

The biological brain implements parallel computations using a complex structure that is different from the conventional von Neumann or load/store computing style. Our brain is a low-power, fault-tolerant, and high-performance machine! It consumes only about 20W and brain circuits continue to operate as the organism needs even when the circuit (neuron, neuroglia, etc.) is perturbed or died. Hardware implementations of spiking neural networks are efficient and effective methods to provide cognitive functions on a chip compared with the conventional load/store computing style. The challenges that need to be solved toward reaching such a neuro-inspired computing paradigm include building a small-size massively parallel architecture with scalable interconnects, low-power consumption, efficient neuro-coding schemes, and lightweight on-chip learning algorithms.

Our goal in this project is to research and develop an ultra-low power spiking neuro-inspired system based on new deep neuronal algorithms and circuits for online on-chip adaptation/learning. Our new system will serve as an adaptive configurable spiking neural network emulation platform with its software environment for systematic parameter explorations.

Research on Fault-tolerant 3D Electro-Photonic Network-on-Chip

Future System-on-Chip (SoC) will contain hundreds of components made of processor cores, DSPs, memory, accelerators, and I/O all integrated into a single die area of just a few square millimeters. Such complex system/SoC will be interconnected via a novel on-chip interconnect closer to a sophisticated network than to current bus-based solutions.This network must provide high throughput and low latency while keeping area and power consumption low.

Our research effort is about solving several design challenges to enable such new paradigm in massively parallel many-core systems. In particular, we are investigating fault-tolerance, 3D-TSV integration, photonic communication, low-power mapping techniques, low-latency adaptive routing, and new applications development.

Related Publications

Previous Projects [最近のプロジェクト]

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