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PhD-Thesis-032015-1

Akram Ben Ahmed, ”High-throughput Architecture and Routing Algorithms Towards the Design of Reliable Mesh-based Many-Core Network-on-Chip Systems”, Ph.D. Thesis, Graduate School of Computer Science and Engineering, University of Aizu, March 2015. [thesis.pdf]

Research Advisor: Prof. Abderazek Ben Abdallah

Abstract

Global interconnects are becoming the principal performance bottleneck for high-performance Systems-on-Chips (SoCs). Since the main purpose of these systems is
to shrink the size of the chip as smaller as possible while seeking at the same time for more scalability, higher bandwidth, and lower latency. Conventional bus-based-
systems are no longer reliable architecture for SoCs due to the lack of scalability and parallelism integration, high latency and power dissipation, and low throughput.
During this last decade, Network-on-Chip (NoC) interconnect has been proposed as a promising solution for future SoC designs. It offers more scalability than the shared-
bus-based interconnection and allows more processors to operate concurrently. Despite the higher scalability and parallelism integration offered by NoC over traditional shared-bus based systems, it is still not an ideal solution for future large-scale SoCs. This is due to some limitations such as high power consumption, high-cost communication, and low throughput. Recently, merging NoC to the third dimension (3D-NoCs) has been proposed to deal with those problems, as it was a solution offering lower power consumption and higher speed. As 3D-NoC architectures started to show their outperformance and energy efficiency against 2D-NoC systems, questions about their reliability to sustain their performance growth begun to arise. This is mainly due to challenges inherited from both 3D-ICs and NoCs: On one side, the complex nature of 3D-IC fabrics and the continuing shrinkage of semiconductor components. Furthermore, the signi cant heterogeneity in 3D chips which are likely to mix logic layers with memory layers and even more complex technologies increases the fault’s probability in a system. On the other side, the single-point-failure nature of NoC introduces a big concern to their reliability as they are the sole communication medium. As a result, 3D- NoC systems are becoming susceptible to a variety of faults caused by crosstalk, electromagnetic interferences, impact of radiations, oxide breakdown, and so on. A simple failure in a single transistor caused by one of these factors may compromise the entire system reliability where the failure can be illustrated in corrupted message delivery, time requirements unsatisfactory, or even sometimes the entire system collapse. In this thesis, we propose 3D-Fault-Tolerant-OASIS (3D-FTO), a robust fault-tolerant 3D-NoC router architecture endorsed with reliable and graceful routing
algorithms. The proposed design handles a large number of faults in the input-buffer, crossbar, and links (which are the most susceptible components to faults in 3D-NoC systems) leveraging the inherent structural redundancy in the architecture to work around errors. Contrary to previous works, the proposed system tolerates multiple faults in a single crossbar with no considerable performance degradation. In addition, the used algorithms are always minimal (as long as there exist one minimal path) and with the aid of Random-Access-Bu er (RAB) mechanism, deadlock-freedom is ensured with no significant area nor power overhead. The proposed 3D-FTO system was synthesized using Synopsys Design Compiler at 45nm technology CMOS process technology and its layout is obtained using Cadence SoC Encounter. The evaluation results showed the ability of 3D-FTO to work around different kinds of faults ensuring graceful performance degradation while minimizing the additional hardware complexity and remaining power-efficient.

Related Publications

  1. Akram Ben Ahmed and Abderazek Ben Abdallah, ”Adaptive Fault-Tolerant Architecture and Routing Algorithm for Reliable Many-Core 3D-NoC systems”, Journal of Parallel and Distributed Computing, 93 (94) 30-43, July 2016.
  2. Akram Ben Ahmed and Abderazek Ben Abdallah, ”Graceful deadlock-free Fault-tolerant Routing Algorithm for 3D-Network-on-Chip Architectures”, Journal of Parallel and Distributed Computing. 74 (4) 2229-2240, April 2014.
  3. Akram Ben Ahmed and Abderazek Ben Abdallah, ”Architecture and Design of High-throughput, Low-latency and Fault Tolerant Routing Algorithm for 3D-Network-on-Chip”, The Journal of Supercomputing, 66 (3) 1507-1532, December 2013.
  4. Akram Ben Ahmed, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, ”Adaptive Error- and Traffic-aware Router Architecture for Electrical 3D Network-on-Chip Systems”, In Proc. of the IEEE 8th International Symposium on Embedded Multicore SoCs (MCSoC-14), Aizu-Wakamatsu, Japan, pp. 197-204, September, 2014.
  5. Akram Ben Ahmed, Achraf Ben Ahmed, and Abderazek Ben Abdallah, ”Deadlock-Recovery Support for Fault-tolerant Routing Algorithms in 3D-NoC Architectures”, In Proc. of the IEEE 7th International Symposium on Embedded Multicore SoCs (MCSoC-13), Tokyo, Japan, pp. 67-72, September, 2012.
  6. Akram Ben Ahmed, Takayuki Ochi, Shohei Miura, A. Ben Abdallah, ”Run-Time Monitoring Mechanism for Efficient Design of Application-specific NoC Architectures in Multi/Manycore Era”, In Proc. of the 6th International Workshop on Engineering Parallel and Multicore Systems, Taichung, Taiwan, pp. 440-445, July, 2013.
  7. Akram Ben Ahmed, Abderazek Ben Abdallah, ”Low-overhead Routing Algorithm for 3D Network-on-Chip”, In Proc. of the 3rd International Conference on Networking and Computing (ICNC-12), Okinawa, Japan, pp. 23-32, December, 2012.
  8. Akram Ben Ahmed, Abderazek Ben Abdallah, ”LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture”, In Proc. of the IEEE 6th International Symposium on Embedded Multicore SoCs (MCSoC-12), Aizu-Wakamatsu, Japan, pp. 167-174, September, 2012.
  9. Akram Ben Ahmed, Kenichi Mori, Abderazek Ben Abdallah, ”ONoC-SPL Customized Network-on-Chip (NoC) Architecture and Prototyping for Data-intensive Computation Applications”, In Proc. of the 4th International Conference on Awareness Science and Technology (iCAST-2012), Seoul, South Korea, pp. 257-262, August,2012.

 

 

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