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Akram Ben Ahmed, ”High-throughput Architecture and Routing Algorithms Towards the Design of Reliable Mesh-based Many-Core Network-on-Chip Systems”, Ph.D. Thesis, Graduate School of Computer Science and Engineering, University of Aizu, March 2015. [thesis.pdf]


Global interconnects are becoming the principal performance bottleneck for high-performance Systems-on-Chips (SoCs). Since the main purpose of these systems is
to shrink the size of the chip as smaller as possible while seeking at the same time for more scalability, higher bandwidth, and lower latency. Conventional bus-based-
systems are no longer reliable architecture for SoCs due to the lack of scalability and parallelism integration, high latency and power dissipation, and low throughput.
During this last decade, Network-on-Chip (NoC) interconnect has been proposed as a promising solution for future SoC designs. It off ers more scalability than the shared-
bus-based interconnection and allows more processors to operate concurrently. Despite the higher scalability and parallelism integration o ffered by NoC over traditional shared-bus based systems, it is still not an ideal solution for future large-scale SoCs. This is due to some limitations such as high power consumption, high-cost communication, and low throughput. Recently, merging NoC to the third dimension (3D-NoCs) has been proposed to deal with those problems, as it was a solution offering lower power consumption and higher speed. As 3D-NoC architectures started to show their outperformance and energy ef ficiency against 2D-NoC systems, questions about their reliability to sustain their performance growth begun to arise. This is mainly due to challenges inherited from both 3D-ICs and NoCs: On one side, the complex nature of 3D-IC fabrics and the continuing shrinkage of semiconductor components. Furthermore, the signi cant heterogeneity in 3D chips which are likely to mix logic layers with memory layers and even more complex technologies increases the fault’s probability in a system. On the other side, the single-point-failure nature of NoC introduces a big concern to their reliability as they are the sole communication medium. As a result, 3D- NoC systems are becoming susceptible to a variety of faults caused by crosstalk, electromagnetic interferences, impact of radiations, oxide breakdown, and so on. A simple failure in a single transistor caused by one of these factors may compromise the entire system reliability where the failure can be illustrated in corrupted message delivery, time requirements unsatisfactory, or even sometimes the entire system collapse. In this thesis, we propose 3D-Fault-Tolerant-OASIS (3D-FTO), a robust fault-tolerant 3D-NoC router architecture endorsed with reliable and graceful routing
algorithms. The proposed design handles a large number of faults in the input-buffer, crossbar, and links (which are the most susceptible components to faults in 3D-NoC systems) leveraging the inherent structural redundancy in the architecture to work around errors. Contrary to previous works, the proposed system tolerates multiple faults in a single crossbar with no considerable performance degradation. In addition, the used algorithms are always minimal (as long as there exist one minimal path) and with the aid of Random-Access-Bu er (RAB) mechanism, deadlock-freedom is ensured with no signi ficant area nor power overhead. The proposed 3D-FTO system was synthesized using Synopsys Design Compiler at 45nm technology CMOS process technology and its layout is obtained using Cadence SoC Encounter. The evaluation results showed the ability of 3D-FTO to work around diff erent kinds of faults ensuring graceful performance degradation while minimizing the additional hardware complexity and remaining power-efficient.


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