Print this Page

Publications

2017

2016

Theses

  • Michael Meyer, Micro-ring Fault-resilient Photonic On-chip Network for Reliable High-performance Many-core Systems-on-Chip”, Ph.D. Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, March 2017.
  • Yusuke Sato, “FPGA Implementation of Heading Reference System Based on Extended Kalman Filter”, Master’s Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, March 2017. [BibTex]
  • Shun Hayamizu, “Automatic Trajectory Selection with Genetic Algorithm for Video Recognition using Time-Space Continuous Dynamic Programming”, Master’s Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, March 2017. [BibTex]
  • Ryunosuke Murakami, “Implementation and Evaluation of Soft-Error Resilience for OASIS Network-on-Chip”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2017. [BibTex]
  • Hiroki Yomogita, “Hardware Implementation and Evaluation of a Soft-Node for Packet-Switched Network-on-Chip”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2017. [BibTex]
  • Shunsuke Mie, “Real-time AHRS circuit from C-based code for System on a programmable chip”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2017. [BibTex]
  • Yuji Murakami, “Design of a Light-Weight Control Network for High-Bandwidth Photonic Network-on-Chip Systems”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2017. [BibTex]
  • Nao Miyamoto, “Video Classification with Numbers of Detected Trajectories Using Time-space Continuous Dynamic Programming”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2017. [BibTex]
  • Kaori Yatsu, “Visualization of Educational Processor in UML”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2017. [BibTex]

2015

  • Khanh N. Dang, Michael Meyer, Yuichi Okuyama, Abderazek Ben Abdallah, Xuan-Tu Tran, “Soft-Error Resilient 3D Network-on-Chip Router“, Proc. of IEEE 7th International Conference on Awareness Science and Technology (iCAST 2015), pp. 84 – 90, Sep. 22-24, 2015. [BibTex]
  • Michael Meyer, Akram Ben Ahmed, Yuki Tanaka, Abderazek Ben Abdallah, “On the Design of a Fault-tolerant Photonic Network-on-Chip,” Proc. of IEEE International Conference on Systems, Man, and Cybernetics (SMC2015), Oct. 9-12, 2015, pp. 821 – 826. [BibTex]
  • Ben Ahmed, Ashraf; Okuyama, Yuichi; Ben Abdallah, Abderazek, “Non-blocking electro-optic network-on-chip router for high-throughput and low-power many-core systems,” in Information Technology and Computer Applications Congress (WCITCA), 2015 World Congress on, vol., no., pp.1-7, 11-13 June 2015 doi: 10.1109/WCITCA.2015.7367068. [BibTex]

Theses

  • Mitsuhiro Nakamura, “Implementation of Matrix Processing Array on a Highly Reliable Network on Chip,” Master’s Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, March 2016. [BibTex]
  • Sean Ito, “Feature Extraction using kernel PCA for Estimation of Calculation Capability with Portable EEG Devices,” Master’s Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, March 2016. [BibTex]
  • Shunsuke Ishikuro, “Arithmetic Resource Optimization for Implementation of a Graph-based Reconfigurable Processor,” Master’s Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, March 2016. [BibTex]
  • Kajikawa, Akihito, Evaluation of Error Detection Mechanism for 3D-OASIS-Network-on-Chip System, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2016.[BibTex]
  • Saito, Ken, Design, and Analysis of Electrical Control Router for Hybrid Photonics NOC System, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2016.[BibTex]
  • Okada, Ryoga, Power and Performance Comparison of Electronic 2D-NoC and Opto-Electronic 2D-NoC, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2016.[BibTex]
  • Ishii, Yosuke, Evaluation of K-nearest neighbor search algorithms forNon-linerState Space Projection on Portable Devices, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2016.[BibTex]
  • Sasamoto, Kazuaki, Video Recognition using Trajectories Parameterized by Trigonometric Functions with Time-Space Continuous Dynamic Programming, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2016.[BibTex]

2014

  • Yuichi Okuyama, Shigeyuki Takano, and Tokimasa Shirai, “Design of a Coarse-grained Processing Element for Matrix Multiplication on FPGA,” IEEE Proceedings of the 8th International Symposium on Embedded Multicore/Many-core SoCs (MCSoC-14), pp.237-241, Sept. 2014. [DOI], [BibTex]

Theses

  • Mitsunari Ishii, Architecture, and Design of an Efficient Router for OASIS 3D Network-on-Chip System, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2015. [slides.pdf]
  • Yuuki Tanaka, Design and Evaluation of Efficient Error Detection Mechanism for OASIS 3D-NoC, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2015. [slides.pdf]. [Technical Report]

2013

  • Toshihiro Sato, Yuichi Okuyama, and Motoki Sakai,”Simulation Study of a P300 Speller for Single-Lead Hybrid BCI,” SICE Annual Conference 2013 (SICE2013), Sep.2013 (Young Author’s Award Finalist)

2012

  • Junko Tazawa, Yuichi Okuyama, Yuichi Yaguchi, Toshiaki Miyazaki, Ryuichi Oka, and Kenichi Kuroda, “Hardware Implementation of Accumulated Value Calculation for Two-Dimensional Continuous Dynamic Programing,” IEEE 6th International Symposium on Embedded Multicore SoCs (MCSoC 2012), DOI 10.1109 /MCSoC.2012.10, Sep. 2012.
  • M. Sakai, Y. Okuyama, T. Sato, D. Wei, “Nonlinear State-Space Projection Based Method to Acquire EEG and ECG Components Using a Single Electrode”, International Journal of Life Science and Medical Research, Vol. 2, Iss. 4, pp. 96-100, 2012.
  • Sakai M, Okuyama Y, Wei D., “Separation of EEG and ECG components based on wavelet shrinkage and variable cosine window,” J Med Eng Technol. 2012 Feb;36(2):135-43, Feb. 2012.
  • Kenichi Mori, OASIS Network-on-Chip Prototyping on FPGA, Technical Report, Adaptive Systems Lab, The University of Aizu, Feb., 2012. PDF
  • R. Okada, Architecture and Design of Core Network Interface for Distributed Routing in OASIS NOC, Technical Report, Adaptive Systems Lab, The University of Aizu, Feb., 2012. PDF

Theses

  • Y. Kimezawa, ”Towards the Design of Dependable Real-Time System for Remote Health Monitoring of Elderly People,  Master’s Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2013. [slides.pdf],  [BibTex]
  • Takayuki Ochi, ”A Quantitative Performance Study of Shared Memory Multicore Systems”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2013.
  • 小林 一樹, Yuichi Okuyama,”A Design ofHigh Performance Transfer API for Portable PCI Express Interface on an FPGA,” Graduation Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2013.
  • 長谷川 徹, Yuichi Okuyama,”Development of an EEG-based Biofeedback System using BCI2000″, Graduation Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2013.

2011

Theses

  • Shohei Miura, ”Design of Parametrizable Network-on-Chip”, ”’Master’s Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2012, 17SM-MT11.
  • 田沢 純子, Yuichi Okuyama,”Hardware Implementation of Accumulated Value Calculation for Two-Dimensional Continuous Dynamic Programming,” Master’s Thesis, The University of Aizu, Feb. 2012.
  • 五十嵐 翔一, Yuichi Okuyama,”A Design Framework for Highly-Portable PCI-Express Interface FPGA Boards,” Master’s Thesis, The University of Aizu, Feb. 2012.
  • 森田 竜平, Yuichi Okuyama,”A Retargetable PROGRAPE System with a PCI-Express Framework,” Master’s Thesis, The University of Aizu, Feb. 2012.
  • 吉田 幸祐, Yuichi Okuyama,”An acceleration method of 2D Continuous Dynamic Programming with Multi-core processor and GPGPUs”, Master’s Thesis, The University of Aizu, Feb. 2012.
  • Tomotaka Kasahara, ”Performance and Complexity Study of Multi-QueueCore Systems”, ”’Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2012, Ref. 15TK-GT11.
  • 加治 良亮, Yuichi Okuyama,”Acceleration of accumulated value calculation for 2D Continuous Dynamic Programming with GPGPU”, Graduation Thesis, The University of Aizu, Feb.2012.
  • 佐藤 俊裕, Yuichi Okuyama,”Evaluation of Error Bound and Processing Time in Approximated Nearest Neighbor Searching for Nonlinear Projective Algorithm,” Graduation Thesis, The University of Aizu, Feb. 2012.

2010

  • Yukihiro Yoshida, Koushi Yamaguchi, Yuichi Yaguchi, Yuichi Okuyama, Ken-ichi Kuroda and Ryuichi Oka, “Acceleration of Two-Dimensional Continuous Dynamic Programming by Memory Reduction and Parallel Processing, IADIS International Conference Applied Computing 2010, pp61-68, Timisoara, Romania, Oct. 2010.
  •  ”Multicore Systems-On-Chip: Practical Hardware/Software Design”, ”’ISBN 978-90-78677-22-2, Author: A. Ben Abdallah, Publishers: World Scientific, 2010,”’
  • Dorothy Maduagwu, Performance Evaluation of Queue Processor Vs. RISC Architecture, MS Thesis, AUST University, 2010.
  • Aminu Mahdi, Effective Dynamic Re-mapping Algorithm for low power Network-on- Chip (NoC), MS Thesis, AUST University, 2010.
  • Dwumfour Abdullai, Designing a Run-time Simulator for QueueCore Processor, MS Thesis, AUST University, 2010.
  • Aliu Sunday Jhon, AFRIHEALTH Care Monitoring System Using Multicore System on Chip Electrocardiography, MS Theis, AUST University, 2010.
  • Arquimedes Canedo, Ben Abdallah Abderazek, and Masahiro Sowa. 2010. Compiling for Reduced Bit-Width Queue Processors. J. Signal Process. Syst. 59, 1 (April 2010), 45-55. DOI=http://dx.doi.org/10.1007/s11265-008-0286-3

Theses

  • Masashi Masuda, ”Produced Order Queue Compiler Design”, Master’s Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2011.
  • Takahiro Uesaka, ”OASIS NoC Topology Optimization with ShortPath Link”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2011, Ref. 11TU-GT10.
  • Yumiko Kimezawa, ”Multicore SoC Architecture for Realtime Data Intensive ECG Processing”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2011.”’9UK-GT10 . Supervisor: Prof. A. Ben Abdallah.
  • 仁木 翔太, Yuichi Okuyama, “GPGPU Acceleration of Smoothed Particle Hydrodynamics Simulation, Graduation Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2011.
  • 前田 和広, Yuichi Okuyama, “Precision Improvement in SPH Simulation Using a Computational Grid, Graduation Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2011.

2009

  • Fumiko OHORI, Yuichi OKUYAMA, Junji KITAMICHI, Kenichi KURODA, and Tsuyoshi HAMADA, “Evaluation of an Image Filtering Algorithm using the Particle Interaction Accelerator on FPGA,” The 24th International Technical Conference on Circuits / Systems, Computers and Communications (ITC-CSCC 2009 ), July 2009.
  • Y. Haga, A. Ben Abdallah, and K. Kuroda, ”Embedded MCSoC Architecture and Period-Peak Detection (PPD) Algorithm for ECG/EKG Processing”, ”’The 19th Intelligent System Symposium (FAN 2009), pp.298-303, Sep. 2009.”’
  • S. Miura, A. Ben Abdallah, and K. Kuroda, ”PNoC – Design and Preliminary Evaluation of a Parameterizable NoC for MCSoC Generation and Design Space Exploration”, ”’The 19th Intelligent System Symposium (FAN 2009), pp.314-317, Sep. 2009.”’
  • K. Mori, A. Ben Abdallah, and K. Kuroda, ”Design and Evaluation of a Complexity-Effective Network-on-Chip Architecture on FPGA”,”’ The 19th Intelligent System Symposium (FAN 2009), pp.318-321, Sep. 2009”’.
  • M. Masuda, A. Canedo, A. Ben Abdallah, ”Efficient Code Generation Algorithm for Natural Instruction Level Parallelism-aware Queue Architecture”,”’ The 19th Intelligent System Symposium (FAN 2009), pp.308-313, Sep. 2009.”’ (Best Presentation Award).
  • A. Canedo, A. Ben Abdallah, and M. Sowa, ”Compiler Support for Code Size Reduction using a Queue-based Processor”, ”’Transactions on High-Performance Embedded Architectures and Compilers, Vol. 2, Issue 4, pp. 269-285, 2009.

Theses

  • Yuuki Omoto, ”Development Environment for Single Chip Computer intended for Queue Computing Development and Education”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2010, Ref. 8YO-GT09.
  • Haga Yasuyoshi, ”Architecture and Design of Application Specific Multicore SoC”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2010, Ref. 7HY-GT09 .
  • Reo Honjoya,”Development ofUser Friendly Assembler for Queue Computers”, ”’Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2010, Ref. 6RO-GT09 .
  • Mori Kenichi, ”Optimizations Techniques and FPGA Prototyping of OASIS Network-on-Chip”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2010, Ref. 5MK-GT09 ”’
  • Miura Shohei,”Architecture and Design of Parameterizable Network-on-Chip”, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2010, Ref. 4MS-MT09.
  • 新沼晴香, Yuichi Okuyama, “proposal of an Automatic Classification Method for Pulse Diagnosis Using Self-Organizing Maps, Graduation Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2010.
  • 吉田幸祐, Yuichi Okuyama, “Acceleration of 2D Continuous Dynamic Programming by Memory Reduction and Parallelization”, Graduation Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2010.

2008

  • T. Maekawa, A. Ben Abdallah, and K. Kuroda, ”Single Instruction Dual-Execution Model Processor Architecture”, ”’Proc. IEEE/IFIP Int’l Conf. on Embedded and Ubiquitous Computing (EUC2008), pp.30-36, Dec. 2008.”’
  • H. Hoshino, A. Ben Abdallah, and K. Kuroda, ”Advanced Optimization and Design Issues of a 32-bit Embedded Processor Based on Produced Order Queue Computation Model”, ”’IEEE/IFIP Int’l Conf. on Embedded and Ubiquitous Computing (EUC2008),pp.16-22, Dec.2008.”’
  • Takahiro Machino, Shin-ya Iwazaki, Yuichi Okuyama, Junji Kitamichi, Ken-ichi Kuroda, and Ryuichi Oka, “Optimizing Two-Dimensional Continuous Dynamic Programming for Cell Broadband Engine Processors,” Japan-China Joint Workshop on Frontier of Computer Science and Technology (FCST) 2008, pp.186-193, Nagasaki, Japan, Dec. 2008.
  • Toshiyuki Ito, Kazuya Mishou, Yuichi Okuyama, and Kenichi Kuroda, “A Hardware Resource Management System for Adaptive Computing on Dynamically Reconfigurable Devices,” Japan-China Joint Workshop on Frontier of Computer Science and Technology (FCST) 2006, pp.196-202, Japan, Nov. 2008.
  • Daisuke Ohwada, Yuichi Okuyama, and Kenichi Kuroda, “Implementation of a Combined Autocorrelation Method for Real-time Tissue Elasticity Imaging on FPGA,” IEEE 8th International Conference on Computer and Information Technology, pp.891-897, Sydney, Australia, July 2008.
  • Kaai Kojima, Yuichi Okuyama, and Kenichi Kuroda, “Arithmetic Precision of the Generalized Hebbian Algorithm for Hardware Implementation,” IEEE 8th International Conference on Computer and Information Technology, pp.886-890, Sydney, Australia, July 2008.
  • A. Canedo, A. Ben Abdallah, and M. Sowa, ”Quantitative Evaluation of Common Subexpression Elimination on Queue Machines”, ”’Proc. IEEE Int’l Sym. on Parallel Architectures, Algorithms, and Networks (I-SPAN 2008), pp.25-30. 2008.”’
  • A. Ben Abdallah, A. Canedo, and K. Kuroda, ”Processor for Mobile Applications”, ”’ISBN: 978-1-60566-046-2, IGI Publishers, 2008.”’
  • M. Akanda, A. Ben Abdallah, and M. Sowa, ”Dual-Execution Mode Processor Architecture”, ”’Journal of Supercomputing, Vol. 44, No. 2, pp. 103-125, 2008.”’
  • Md, M. Akanda, Architecture and Hardware Design of a Dual-Execution mode Processor Based on Produced Order Queue Execution Model, Doctor Thesis, UEC, 2008/3.

Theses

  • 猪狩修平, Yuichi Okuyama, “Implementation of Dynamic Instruction Set Computer using Dynamic Partial Reconfiguration Technology,” Graduation Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2009.
  • 志賀瑞穂, Yuichi Okuyama, “Study on Convolution Systolic Array Adopted to the Digital Signal Processors on FPGA,” Graduation Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2009.
  • 八巻翔, Yuichi Okuyama, “Design of Efficient Interface for RapidMatriX Considering Size and Locality of Matrix Multiplication,” Graduation Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2009.

2007

  • A. Canedo, A. Ben Abdallah, and M. Sowa, ”A New Code Generation Algorithm for 2-offset Producer Order Queue Computation Model”, ”’Journal of Computer Languages, Systems & Structures, Vol. 34, Issue 4, pp. 184-194, 2007”’
  • A. Ben Abdallah, and M. Sowa, ”Advanced Power Management Techniques for Mobile Communication Systems”, ”’Journal of Computer Research, Vol. 14, No.2, pp. 109-128, 2007”’
  • Mushiq Akanda, A. Ben Abdallah, and M. Sowa, ”Dual-Execution Mode Processor Architecture for Embedded Applications”, ”’Journal of Mobile Multimedia, Vol. 3, No. 4, pp. 347-370, 2007.”’
  • Y. Nakanishi, A. Canedo, A. Ben Abdallah, and M. Sowa, ”Optimizing Reaching Definitions Overhead in Queue Processors”, ”’Journal of Convergence Information Technology, 2007, Vol. 2, No. 4, pp. 36-40, 2007.”’
  •  ”Multicore Systems on Chips”, ”’ISBN: ISBN 978-81-7895-258-1, Editor (and one of the Authors): A. Ben Abdallah, Publishers: Signpost, 2007.”’
  • A. Ben Abdallah, and M. Sowa, ”Efficient Design Methodology and Synthesizable Core for Multicore SoCs”, ”’ISBN: 978-81-7895-258-1, Signpost Publishers, 2007”’
  • A. Ben Abdallah, and M. Sowa, ”Buffer Design in Packet Switched Networks for MCSoCs Applications”, ”’ISBN: 978-81-7895-258-1, Signpost Publishers, 2007.”’
  • A. Ben Abdallah, and M. Sowa, ”Power Optimization Techniques for Mobile Multicore SoCs”, ”’ISBN: 978-81-7895-258-1, Signpost Publishers, 2007.”’
  • A. Ben Abdallah, T Yoshinaga, and M. Sowa, ”Mathematical Model for Multiobjective Synthesis of NoC Architectures”, ”’IEEE Proc. of the 36th International Conference on Parallel Processing, Sept., 2007.”’
  • A. Canedo, A. Ben Abdallah, and M. Sowa, ”Queue Register File Optimization Algorithm for QueueCore Processor”, ”’Proc. IEEE 19th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), pp. 169-176, 2007.”’
  • A. Canedo,A. Ben Abdallah, and M. Sowa, ”An Efficient Code Generation Algorithm for Code Size Reduction using 1-offset P-Code Queue Computation Model”, ”’Proc. IFIP International Conference on Embedded and Ubiquitous Computing (EUC07), pp. 196-208, 2007”’
  • A. Canedo, A. Ben Abdallah, and M. Sowa, ”Compiler Framework for an Embedded 32-bit Queue Processor”, ”’Proc. of the International Conference on Convergence Information Technology (ICCIT07), Gyeongju, South Korea, pp. 877-884, 2007.”’

2006

  • A. Ben Abdallah, Sotaro Kawata, and M. Sowa, ”Design and Architecture for an Embedded 32-bit QueueCore”, ”’Journal of Embedded Computing, Special Issue in embedded single-chip multicore architectures, Vol. 2, No. 2, pp. 191-205, 2006.”’
  • A. Ben Abdallah, and M. Sowa, ”Advanced Power Reduction Techniques in Mobile Computing Systems”, ”’ISBN:1-60021-207-7, Nova Science Publishers, 2006.”’
  • A. Ben Abdallah, T. Yoshinaga, and M. Sowa, ”Scalable Core-Based Methodology and Synthesizable Core for Systematic Design Environment in Multicore SoC (MCSoC)”, ”’Proc. IEEE 35th International Conference on Parallel Processing Workshops, Aug. 14-18th, pp. 345-352, 2006.”’

2005

  • T. Viet, T. Toshinaga ,A. Ben Abdallah, and M. Sowa, ”Construction of Hybrid MPI-OpenMP Solutions for SMP Clusters”, ”’IPSJ Transactions on Advanced Computing Systems, Vol.46, pp.25-37, Jan. 2005.”’
  • Toshiyuki Ito, Yuichi Okuyama, Junji Kitamichi, Kenichi Kuroda, “A master-slave adaptive load-distribution processor model on PCA,” The 12th Reconfigurable Architectures Workshop (RAW 2005), April 2005.
  • M. Sowa, A. Ben Abdallah, and T. Yoshinaga, ”Processor Architecture Based on Produced Order Computation Model”, ”’Journal of Supercomputing, Vol. 32, No. 3, pp. 217-229, June 2005.”’
  • A. Ben Abdallah, M. Arsenji, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core”, ”’Proc. of International Conference on Embedded and Ubiquitous Computing (EUC2005), LNCS Vol.3824, pp. 340-349, 2005.”’
  • M. Akanda, A. Ben Abdallah, S. Kawata, and M. Sowa, ”An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture”, ”’Proc. of International Conference on Embedded and Ubiquitous Computing (EUC2005), LNCS Vol.3824, pp. 77-86, Dec. 2005.”’
  • A. Markovskij, A. Ben Abdallah, S. Kawata, and M. Sowa, ”Architecture of Produced-order Parallel Queue Processor: Preliminary Evaluation”, ”’Proc. of the 38th International Symposium on Microarchitecture (MICRO-38), Nov. 2005.”’
  • A. Ben Abdallah, T. Yoshinaga, and M. Sowa, ”Rapid FPGA Prototyping of a Queue Processor Core for Embedded Computing”, ”’Proc. of 67th Conf. of Information Processing Society of Japan, March 2~4, 2005.”’
  • Ta Quo Viet, T. Yoshinaga, and A Ben Abdallah, ”Performance Enhancement for Matrix Multiplication on an SMP PC Cluster”, ”’Summer United Workshops on Parallel, Distributed and Cooperative Processing, August 2005. ”’

2004

  • A. Ben Abdallah, Markov Arsenji, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Queue Processor for Novel Queue Computing Paradigm Based on Produced Order Scheme”, ”’Proc. IEEE of the 7th High-Performance Computing and Grid in Asia Pacific Region (HPCAsia2004), pp. 169-177, July 2004.”’
  • Shigeta, L.-Q. Wang, N. Yagishita, A. Ben Abdallah, T. Yoshinaga, and M. Sowa, ”QJava: Integrate Queue Computational Model into Java”, ”’Proc. of the Joint Japan-Tunisia Workshop on Computer Systems and Information Technology (JT-CSIT’04), July 2004.”’
  • A. Markovskij, M. Sowa, A. Ben Abdallah, S. Shigeta, and T. Yoshinaga, ‘7Design of Producer-Order Parallel Queue Processor Architecture”, ”’Proc. of International Workshop on Modern Science and Technology (IWMST 2004), September 2-3, 2004.”’
  • M. Akanda, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”High-performance Hybrid Processor Architecture with Efficient Hardware Usability”,”’ Proc. of International Workshop on Modern Science and Technology (IWMST 2004), September 2-3, 2004.”’
  • H. Sasaki, Y. Okumura, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Theoretical Evaluation of Simultaneous Multi threading Parallel Queue Processor Architecture”, ”’Proc. International Conference on Circuits/Systems, Computers, and Communications, July 2004.”’
  • A. Ben Abdallah, M. Arsenji, K. Kiuchi, M. Akanda, S. Shigeta, T. Yoshinaga, and M. Sowa, ”PQPpfB: Parallel Queue Processor Architecture in Verilog-HDL”, ”’Proc. of 66th Information Processing Society of Japan, pp. 3F-4, March 2004.”’
  • T. Viet, T. Toshinga, A. Ben Abdallah, and M. Sowa, ”Optimization for Hybrid MPI-OpenMP Programs on a Cluster of SMPs”, ”’SACSIS 2004”’.
  • A. Musfiquzzaman, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Queue Computation Mechanism For Parallel Execution in Parallel Queue Processor”, ”’Proc. Of Information Processing Society of Japan, Vol. 60, pp. 3F-4, 2004.”’

2003

  • Toshiyuki Ito, Kentaro Ono, Mayumi Ichikawa, Yuichi Okuyama, and Kenichi Kuroda, “Reconfigurable Instruction-Level Parallel Processor Architecture,” ACSAC2003(LNCS 2823), pp.208-220, Sep.2003.
  • A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”On the Design of a Register Queue Based Processor Architecture (FaRM-rq)”, ”’Proc. of the International Symposium on Parallel and Distributed Processing and Applications (ISPA 2003), pp.248-262, July 2003.”’
  • L. Q. Wang, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”QJAVAC: Queue-Java Compiler Design for High Parallelism Queue Java Bytecode”, ”’Proc. of International Technical Conference on Circuits/Systems, Computers, and Communications (ITC-CSCC2003), pp. 900-903, July 2003.”’
  • A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Architectural Issues in the Design of a High-Performance Parallel Queue Processor”, ”’Proc. of 4th Tunisia-Japan Symposium on Science and Technology (TJASSST2003), April 2003.”’
  • Tao. Q. Viet, T. Yoshinaga, A. Ben Abdallah, and M. Sowa, ”A Hybrid MPI-OpenMP Solution for a Linear System on a Cluster of SMPP”, ”’SACSIS03, pp.299-306, 2003.”’
  • A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Reduced Bit-Width Instruction Set Architecture for Q-mode Execution in Hybrid Processor Architecture (FaRM-rq)”, ”’Proc. of Information Processing Society of Japan, pp. 19-23, June 2003.”’
  • L. Wang, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Fast, Effective Instruction Generation Algorithm For Queue-Java Compiler (QJAVAC)”,”’ Proc. of Information Processing Society of Japan, Vol.2003, No.40, pp.55-60, 2003. ”’
  • L. Wang, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”An Ambiguous Context-Free Grammar for Deterministic Parsing In Queue-Java Compiler”, ”’Proc. of Information Processing Society of Japan, Vol.2003, No.62, pp.7-12, 2003. ”’
  • L. Wang, A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”QJAVAC: Queue-Java Compiler Design for High Parallelism Queue Java”, ”’Proc. of IIEICE Technical Conference, 2003”’.
  • T. Q. Viet, T. Yoshinaga, A. Ben Abdallah, and M. Sowa, ”A Hybrid MPI-OpenMP Solution for a Linear System on a Cluster of SMPs”,”’ Proc. of Symposium on Advanced Computing Systems and Infrastructures, pp.299-306, 2003. ”’

2001-02

  • A. Ben Abdallah, S. Shigeta, T. Yoshinaga, and M. Sowa, ”Complexity Analysis of a Functional Assignment Register Microprocessor”, ”’Proc. of the Int. Workshop on Modern Science and Technology (IWMST02), pp.116-123, Sep. 2002”’.
  • Nattha Sretasereekul, Yuichi Okuyama, Hiroshi Saito, Masashi Imai, Kenichi Kuroda and Takashi Nanya, “Flexible Partitioning of CDFGs for Compact Asynchronous Controllers,” ITC-CSCC2002, Vol.3, pp.1724-1727, Jul.2002.
  • A. Ben Abdallah, K. Nikolova, and M. Sowa, ”FARM-Queue Mode: On a Practical Queue Execution Model”, ”’Proc. of the Int. Conf. on Circuits and Systems, Computers and Communications, pp.939-944, July 2001.”’
  • Kiriuka Nikolova, A. Ben Abdallah, and M. Sowa, ”Dynamical Critical Path Parallelism-Independent Scheduling Algorithm for Distributed Computing Systems”, ”’Proc. Of the International Technical Conference on Circuits and Systems, Computers and Communications, pp. 929-934, July 2001.”’
  • A. Ben Abdallah, K. Nikolova T. Yoshinaga, and M. Sowa, ”FARM QUEUE MODE: On a Practical Queue Execution Model (QEM)”, TIWSS’01, October 2001.”’

2000

  • A. Ben Abdallah, Mudar Sarem, and M. Sowa, ”Dynamic Fast Issue Mechanism (DFI) for Dynamic Scheduled Processors”, IEICE Transactions on Fundamental of Electronics, Communications, and Computer Science, Vol. E83-A No.12 pp.2417-2425, Dec. 2000.
  • A. Ben Abdallah, K. Nikolova, and M. Sowa, ”FARM-Queue Execution Model: Towards an Alternative Computing Paradigm”, ”’Proc. of IPSJ Symposium, Yokohama pp.99-100, March 2000.”’
  • A. Ben Abdallah, M. Sarem., and M. Sowa, ”Acyclic DFG on a Queue Machine”,”’ Proc. of JSPP, Tokyo, pp.119-120, 2000.”’
  • A. Ben Abdallah, and M. Sarem., ”Instruction Scheduling System for Super scalar Processor”, ”’JSPP, Tokyo, pp.161, Apr. 2000.”’
  • Y. Okuyama, K. Kuroda, and K. Oguri, “Design Methodology for Applications Based on an Asynchronous Reconfigurable Architecture,” IS2000, pp.356-361, Nov.2000.
  • A. Ben Abdallah, Mudar Sarem, and M. Sowa, ”Dynamic Fast Issue Mechanism (DFI) for Dynamic Scheduled Processors”, ”’IEICE transactions on Fundamental of Electronics, Communications and Computer Science, Vol. E83-A No.12 pp.2417-2425, Dec. 2000.”’
  • Ryoga Okada,Power and Performance Comparison of Electronic 2D-NoC and Opto-Electronic 2D-NoC, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu}, March 2016. Technical Report.pdf

1996-1999

  • A. Ben Abdallah, and M. Sowa, ”DRA: Dynamic Register Allocator Mechanism for FaRM Microprocessor”, ”’Proc. of the 3rd International Workshop on Advanced Parallel Processing Technologies (APPT’99), pp.131-136, October 1999.”’
  • A. Ben Abdallah, M. Sarem, and M. Sowa, ”A Survey on the advances of Disc I/O performance metrics”, ”’Proc. of International Conference on Robotics, Vision and Parallel Processing, pp. 522-527, July 1999.”’
  • A. Ben Abdallah, A. Kazi, and L. L. Shan, ”Multi-Function Interface Board for Teaching Topics and Development System”, ”’APST97, Yata, PRC. pp.134-139, Sep. 1997.”’
  • L. L. Shan, L. Liu, and A. Ben Abdallah, ”The Master-Slave Two Level Distributed Microcomputer Measuring and Monitoring System”, ”’ISMTIT, Japan, pp. 161-164, 1996”’

Books

  • A. Ben Abdallah (Author), Advanced Multicore Systems On-Chip: Architecture, On-Chip Network, Design, Publisher: Springer-Japan, (Q4, 2017).
  • A. Ben Abdallah (Author), Multicore Systems On-Chip: Practical Hardware/Software Design, 2nd Edition, Publisher: Atlantis, 2013, ISBN-13:  978-9491216916.
  • A. Ben Abdallah (Author): Multicore Systems On-Chip: Practical Hardware/Software Design, Publisher: Atlantis, 2010, ISBN 978-90-78677-22-2.
  • A. Ben Abdallah (Editor and one of the authors): Multicore Systems on-Chips, Publishers: Signpost, 2007, ISBN: ISBN 978-81-7895-258-1.

Technical Reports

  • H. Hoshino, QC-2 Data Path, Technical Report, ASL Systems Architecture Group, School of Computer Science and Engineering, The University of Aizu, Oct. 2009
  • A. Ben Abdallah, QueueCore – The Strong Wave!, Technical report, Network Computing Laboratory, Graduate School of Information Systems, The University of Electro-communications, May 2007
  • A. Ben Abdallah, QueueCore Instruction Set Architecture, Technical Report, Parallel/Distributed Systems Laboratory, Graduate School of Information Systems, National University of Electro-communications, January 2003.
  • A. Ben Abdallah, QC-1 Processing Stages Algorithms, Technical Report, Parallel/Distributed Systems Laboratory, Graduate School of Information Systems, National University of Electro-communications, 2003.
  • Kenichi Mori, OASIS Network-on-Chip Prototyping on FPGA, Technical Report, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2012, Technical Report
  • Akram Ben Ahmed, On the Design of a 3D Network-on-Chip for Many-core SoC [#k7419422] Technical Report, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2012, Technical Report
  • Ryuya Okada, Architecture and Design of Core Network Interface for Distributed Routing in OASIS NOC, Technical Report, School of Computer Science and Engineering, The University of Aizu, Feb. 2012 Technical Report
  • Vu Huy The, OASIS NOC Survey, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, October 18, 2016

 

 

——————————————————————————————————————————————————————————————————————————
Author: Abderazek Ben Abdallah
Publisher: Springer, 2017
Hardcover: 273 pages
Language: English
ISBN-13: 978-9811060915
[Preface] [Contents], Available from Springer and Amazon
Author: Abderazek Ben Abdallah
Publisher: Atlantis, 2013
Hardcover: 260 pages
Language: English
ISBN-13: 978-9491216916
[Preface] [Contents], Available from Springer and Amazon
 
Author: Abderazek Ben Abdallah
Publisher: Atlantis, 2010
Hardcover: 200 pages
Language: English
ISBN-10: 9078677228
Available from World Scientific  and Amazon

Permanent link to this article: http://adaptive.u-aizu.ac.jp/?page_id=111